FPGA multiplication using Verilog

[Altera_Forum]

I am new here. For FPGA multiplication in Verilog, do I need to extend the sign bit for signed numbers before I do the multiolication? Or, there is a library that could take care of this part for me automatically just as how we do the multiplication using VHDL?

[Altera_Forum]

You just need to declare the inputs and outputs as signed types and the appropriate hardware will be created. Take a look at the verilog templates built into Quartus, I recall seeing a signed multiplier being included.