Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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FPGA symbol creation

Altera_Forum
Honored Contributor II
‎03-02-2009 12:20 PM
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Dear all, 

 

I would like to know whether FPGA symbol can be created using mentor graphics design capture s/w and Quartus 8.1 Quartus has generated a EDA netlist file. It is stated that modelsim i/o designer s/w is needed for FPGA symbol creation. But i don't have a licensed version. Will the evaluation version be sufficient for symbol creation? Can the symbol be created using design capture s/w also. Please suggest me. 

 

 

Thanks & regards 

praveen
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Altera_Forum
Honored Contributor II
‎03-12-2009 11:22 AM
346 Views

Yes, it can be done. 

 

I have a clunky home-brewed bit of C which will generate DC/DV symbols from a text file which can reasonably easily be hacked from Altera's pin list. 

 

It produces a text file output that ASCII-IN can import into a DC/DV library. 

 

IO designer is quite nice, but comes with a fairly hefty price tag.
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