FSM behaving strangely

Altera_Forum · ‎01-18-2008

I have a simple set of VHDL code that steps through an FSM doing certain things. It compiles fine and I can design my test waveform. However when I run the simulation some of the pins don't show up in the results and outputs that are goverened by what happens to those pins don't get any values.

Specifically the pins that don't show up are the isLoadInstruction,isStoreInstruction etc.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all ;
USE ieee.std_logic_unsigned.all;
ENTITY fsm IS
    PORT(clock,reset,isLoadInstruction,isStoreInstruction,isAddInstruction,isMultiplyInstruction,regSource1,regSource2,regDestination: IN STD_LOGIC;
		 PC: BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0);
         readInstructionMemory,readRegs,writeRegs,performAdd,performMultiply,readDataMemory,writeDataMemory: OUT STD_LOGIC);
END fsm;
ARCHITECTURE Behavior OF fsm IS
TYPE State_type IS(A,B,C,D,E);
SIGNAL state: State_type;
BEGIN
    PROCESS(clock)
    BEGIN
        IF Reset = '1' THEN
            state<=A;
			PC<="0000000000000000";
        ELSIF(clock'EVENT AND clock='1') THEN
            CASE state IS
            WHEN A=>
				readInstructionMemory <= '1';
				readRegs <= '0';
				writeRegs <='0';
				performAdd <= '0';
				performMultiply<='0';
				readDataMemory<='0';
				writeDataMemory<='0';
				state<=B;
			WHEN B=>
				readRegs <= '1';
				PC <= PC + 1;
				readInstructionMemory <= '0';
				writeRegs <='0';
				performAdd <= '0';
				performMultiply<='0';
				readDataMemory<='0';
				writeDataMemory<='0';
				state<=C;
			WHEN C=>
				IF isAddInstruction ='1' OR isLoadInstruction='1' OR isStoreInstruction ='1' THEN
					performAdd<='1';
				ELSE performAdd<='0';
				END IF;
				IF isMultiplyInstruction ='1' THEN
					performMultiply<='1';
				ELSE performMultiply<='0';
				END IF;
				readRegs <= '0';
				readInstructionMemory <= '0';
				writeRegs <='0';
				readDataMemory<='0';
				writeDataMemory<='0';
				state<=D;
			WHEN D=>
				IF isLoadInstruction='1' THEN
					readDataMemory<='1';
				ELSE readDataMemory<='0';
				END IF;
				IF isStoreInstruction ='1' THEN
					writeDataMemory<='1';
				ELSE writeDataMemory<='0';
				END IF;
				readRegs <= '0';
				readInstructionMemory <= '0';
				writeRegs <='0';
				performAdd<='0';
				performMultiply<='0';
				state<=E;
			WHEN E=>
				IF isStoreInstruction='1' THEN
					writeRegs<='0';
				ELSE writeRegs<='1';
				END IF;
				readRegs <= '0';
				readInstructionMemory <= '0';
				performAdd<='0';
				performMultiply<='0';
				readDataMemory<='0';
				writeDataMemory<='0';
				state<=A;
            END CASE;
        END IF;
    END PROCESS;
END Behavior;

Altera_Forum · ‎01-18-2008

Bit of a guess here but if you are using ModelSim try the -novopt option.

vsim -novopt ect...

Altera_Forum · ‎01-18-2008

How are you simulating? Are you simulating with the Quartus II simulator or Modelsim? Are you simulating a gate-level VO or VHO or RTL? What do you mean "pins don't show up"? What version of Quartus are you using? BTW, you want to add the reset signal to your sensitivity list; otherwise, your design won't simulate correctly in Modelsim.

Altera_Forum · ‎01-18-2008

I'm simulating in Quartus. I'm not doing anything special, just running a timing simulation. Here's what it's showing me. The top picture is the result and the bottom picture is what I designed as a simulation. Some of the pins are missing from the results. Some of them are tough to read but its obvious that some are missing

http://img156.imageshack.us/img156/478/helppq5.png

Altera_Forum · ‎01-18-2008

Hello,

I don't get 'X' in output when simulating your design, even when omitting the reset as you did. Could be due to different device family, Quartus version or global synthesis options. However, with correct reset, no 'X' should be seen, unconditionally.

Regards,

Frank

Altera_Forum · ‎01-19-2008

I concur with Frank. I approximated the same VWF and simulated your design using Stratix and Stratix II devices. At first I thought you may have a setup violation, but it appears the maximum setup time for any register was ~ 3ns. I think there's something amiss. If I had to guess, the design is simulating without any stimulus to those missing input pins. They simply float at X and thus any registers whose input cones depend on those inputs go to X whenever the registers MIGHT depend on the inputs. In fact, if I simply delete those pins from my stimulus, I see what you're seeing.

Are you sure you're using the right VWF? Try re-creating it. Do you see any odd messages?

Altera_Forum · ‎01-19-2008

The code posted should be cleaned up a bit...

BEGIN

PROCESS(clock)

BEGIN

IF Reset = '1' THEN

state<=A;

PC<="0000000000000000";

ELSIF(clock'EVENT AND clock='1') THEN

BEGIN

PROCESS(clock, reset)

BEGIN

IF Reset = '1' THEN

state<=A;

PC<="0000000000000000";

readinstructionmemory <= '0';

readregs <= '0';

writeregs <= '0';

performadd <= '0';

performmultiply <= '0';

readdatamemory <= '0';

writedatamemory <= '0';

ELSIF(clock'EVENT AND clock='1') THEN

Also, the simulation should have a reset condition(set reset to '1' for a couple clocks and then drop it low, assuming thats what will actually happen). It's good practice to init all outputs/buffers and signals with the reset to ensure predictability.

Altera_Forum · ‎01-20-2008

I fixed it. I think it may have been doing the wrong simulation but it works now.