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I'm using SynplifyPro as input for Quartus. the input is therfore a vqm file. Synplify has made a one hot encoding (real one hot).
When analyzing the statemachine with signaltab is shows an other state sorting (probably the quartus onehot). When further analysing I saw that Quartus did not recognize the statemachines (it does when using the same vhdl I used as input for SynplifyPro). Why doesn't Quartus not recognize the statemachines from a vqm input file? Second question why does Quartus change the state coding (I would expect is only routes the input from synplify not optimizing anymore) from synplify?링크가 복사됨
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1) State-machines are recognized at a high-level, i.e. analyzing a case-statement. The .vqm is a low-level netlist of LUTs/FFs, etc. Quartus can't see the same things. That being said, Synplify should have already done all the necessary state optimizations as well as downstream optimizations that Quartus would have done.
2) I imaging Synplify is doing the Altera one-hot synthesis. The reason this is done is that all registers power-up to 0. "Altera one-hot" just means the first state is all 0s, and so when decoding the lsb, you just invert the decode, i.e. if it's 0 it's active, if it's 1 it's not: 0000 0011 0101 1001 Synplify can't get around the initial state having to be all 0s. So I'm sure it does the same thing. (So I think Synplify is doing everything you want)- 신규로 표시
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The reason i thought it was quartus was when i looked in the rtl view in synplify i see a true one hot. I cant see the state encoding in the technology view ( i think).
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The RTL view reflects the source, not what it gets synthesized too. It could probably get mapped to various SM encodings but still look the same in the RTL view.
