Failed to simulate project that contains VQM file

[Altera_Forum]

Using Modelsim-Altera Starter edition I failed to simulate project that contains VQM file. 

All output signals from VQM file are drawn red U (undefined). This happened when performing from Quartus II 10.1sp1 Web Edition: Tools => Run EDA simulation tool => EDA RTL simulation  Best regards,  Rami

[Altera_Forum]

--- Quote Start ---  Using Modelsim-Altera Starter edition I failed to simulate project that contains VQM file. All output signals from VQM file are drawn red U (undefined). This happened when performing from Quartus II 10.1sp1 Web Edition: Tools => Run EDA simulation tool => EDA RTL simulation  Best regards,  Rami  --- Quote End ---    Hi,  there are serveral reasons for getting undefined signals. Did you try an RTL simulation upfront ? Do you get warning about timinf violations during the simulation of the VQM file ? Did you have a reset implemented in your design ? Another reason could be that parts of your logic is removed by the synthesis tool. Have a look to the result files of the Quartus run.  Kind regards  GPK

[Altera_Forum]

I suspect the reason is using Quartus Web Edition, because: 

1. Implementing the project with VHD file is O.K 2. I got a warning: "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." but I did not use directly this feature I suspect that using VQM file force you to use this feature. 3. I got a warning:  "Port Connectivity Checks…Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;" But I did and I use the same declaration in VHD file case. You are gently requested to confirm or to reject my assumption.   Best regards,  Rami

[Altera_Forum]

--- Quote Start ---  I suspect the reason is using Quartus Web Edition, because: 1. Implementing the project with VHD file is O.K 2. I got a warning: "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." but I did not use directly this feature I suspect that using VQM file force you to use this feature. 3. I got a warning:  "Port Connectivity Checks…Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;" But I did and I use the same declaration in VHD file case. You are gently requested to confirm or to reject my assumption.   Best regards,  Rami  --- Quote End ---    Hi Rami,  it looks like that my last reply is not send out. It looks to me tha tyour problem is related to point 3. Have look to the part in your design where you are using the instance. Are all ports well connected ?  Kind regards  GPK