Hi,
It's the first time that I'm trying to use the BFMs so I decided to try and simulate the PIO or SPI IP cores that come with Qsys.
I used the tutorial on the User Guide Avalon Verification IP Suite to simulate the FIFO and it worked and now I'm trying to do the same with those cores.
I added the PIO core and exported all the interfaces and tried to generate a verilog testbench with standard BFMs.
I'm getting an error saying that Error: pio-32BITS_inst_spi_0_spi_control_port_bfm.m0: master without waitrequest must match parameters and ports of slave pio-32BITS_inst.spi_0_spi_control_port.
and when I try to generate the testbench for the SPI core I get the same error and an additional error saying Error: pio-32BITS_tb.pio-32BITS_inst_spi_0_spi_control_port_bfm.m0: pio-32BITS_inst.spi_0_spi_control_port (0x0..0x1f) is outside the master's address range (0x0..0xf).
What am I doing wrong? I thought the generation would be able to deal with a slave that doesn't have a waitrequest signal and I'm really not sure what to do with the second error.
Thanks in advance,
Chen
