Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Feeding a PLL with a global clock

Altera_Forum
Honored Contributor II
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Does TimeQuest take into account the added delay caused by feeding a PLL with a global clock?

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Altera_Forum
Honored Contributor II
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Does TimeQuest use it in it's analysis? Yes, so all analysis is correct. 

Does the PLL compensate for it? No, so the the clock will be delayed in time and will suffer the PVT variation of that global. 

Naturally, it is suggested to drive the PLL directly with one of its dedicated clock pins. But there are plenty of cases where you have to drive it with a global and it works out all right.
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Altera_Forum
Honored Contributor II
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Does TimeQuest use it in it's analysis? Yes, so all analysis is correct. 

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To see this, use -detail full_path for report_timing or set "Detail level" to "Full Path" in the Report Timing dialog box. You'll see everything in the clock path including what is between the clock device input pin and the PLL.
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