Find parameter names on an an entity

[Altera_Forum]

Hi, 

 can someone please tell me how to find the (internal?) parameter names that Quartus uses?  For example, when I was looking for help with creating clocks for TimeQuest for an LPM_Counter, I was pointed to things like : {lpm_counter0:Clock_Divider|lpm_counter:LPM_COUNTER_component|dffs[4]} as the clock target Where lpm_counter0 is a custom LPM counter type Clock_Divider is the instance name And dff[4] is the port that I want to write the counter to.  However, I don't know how I could have found this for myself. The LPM_Counter has ports name CLK and q[0..x], it turns out that dffs[4] is equivalent to q[4], but how would I know that? Where is dffs[] defined?  My specific problem at the moment is that I have an input pin that is used in a small piece of custom VHDL. The output from the VHDL block is used as the clock input for a 74273 function block TimeQuest identifies the input pin name as a clock signal that I need to create a clock for. So, I assume that I need to create a clock for the CLK port of the 74273  Using the Counter example, I guess that I need something like the  Block type (74273?) : Instance Name | [some attribute name][some index name]?  Is there a Quartus manual or help file that tells me how I can find parameter names on blocks that are different to those shown on the parameters/pins display?  regards Dave

[Altera_Forum]

It's best not to think of clocks as "block specific". For most designs you: 

1) Put a create_clock assignment on the clocks coming into top-level I/O ports. 2) Call derive_pll_clocks, which constrains the PLL outputs and transceiver clocks. That's it. If you have ripple clocks(a register that drives the clock port of another register) then you can put a create_generated_clock assignment on that, and you can also put generated clocks on gated clocks(clocks going through combinatorial logic). But you need to be careful, as a these clocks are both considered bad design practice unless you absolutely know what you're doing. An LPM_COUNTER should not be driving the clock port of other logic. Instead that other logic should be driven by the main clock(same one that drives the counter) and the counter just provides synchronous input to this downstream logic. This is general practice and hence most blocks don't need to say explicitly what is in them so you can apply a clock. That being said, if you want to see the names inside, I would suggest the RTL Viewer and the View -> Utility Window -> Node Finder. Good luck.

[Altera_Forum]

Hi,  

 thanks for the reply.  Unfortunately, I am using a (very old) CPLD, an EPM7128S, it does not have PLL clocks (at least, I don't think so).  Off to check out the Node Finder though - cheers  regards Dave