Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Finding FPGA designers and best practices for Quartus projects under Git?

JSambrook_CSSI_FPGA
New Contributor I
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Hello -

 

Recently, I purchased a Stratix 10 GX development board (L-tile variant) and the one year license for the Quartus Prime Pro tools. I have two questions I could use some help with:

 

1. It's mostly been great, but from time to time I could use the advice of more experienced FPGA developers.  I have had some success in hiring them on a contract basis off of Upwork. I'm wondering if there are other boards, or boards sponsored by Intel, where I could find individuals with experience with Quartus and Intel / Altera that are open to remote contract work?

 

2. I would also welcome advice on using Git with Quartus to version my FPGA designs. Are a set of best practices recommended by Intel documented anywhere? I know about making project archives, but they don't really facilitated the use of Git and it's capabilities.

 

Best Regards,

 

John Sambrook

Common Sense Systems, Inc.

 

john@common-sense.com

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ShengN_Intel
Employee
66 Views

Hi,


Check this link https://community.intel.com/t5/Intel-Quartus-Prime-Software/Version-control-for-the-Quartus-project/...

Basically following files are required under version control:

  • .qpf 
  • .qsf 
  • .qsys ( Helps to regenerate your QSYS design. ) 
  • .sopcinfo ( required by software team ) 
  • .sof 
  • Verilog files designed by you ( Files generated by QSYS don't seem to be required there on repository as they will be generated each time you regenerate your Qsys system. So you may not wish to upload synthesis folder on repository. ) 
  • Verilog files generated by Megawizard plug in manager.( As it will contain information about customization of particular mega function. ) 
  • .pin file ( Contains information about all pins in your design. Although it can be eliminated, it may be useful. ) 
  • .sdc file which you have prepared.( SDC files auto generated by Quartus may be ignored. ) 


Probably have to save the .qsys file and all the individual .ip files used in the project. This has been made easy by archiving the whole Platform Designer into a single .zip or .tcl file, here are some guidance:

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/saving-systems.html

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/archiving-systems.html

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/including-systems-in-project-a...


Check this link https://community.intel.com/t5/Programmable-Devices/Prime-Pro-Edition-Source-files-meaning-of-folder...

As far as revision control, using the project archiving feature is the easiest way to manage it to make sure all files get included.


Regards,

Sheng


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