Forming a tightly coupled memory system in Qsys

[Altera_Forum]

Hey, 

 I am trying to generate a custom component which is tightly coupled with the onchip memory. The problem is that the qsys exposes only the port of the onchip memory rather than the individual signals which make it up. Is there any way to interface to the individual signals of the port in qsys or any other way, where i dont have to modify by hand , after it generates the files.

[Altera_Forum]

I thought there was an option in qsys (but not sopc) to expose the signals for the second port of M9K (etc) memory blocks.

[Altera_Forum]

I am not able to find that option if there is one. I was looking at tcl_component_desicription as a way, but feels like it will take some time to get my head around it. I need to expose those signals in qsys or in some other way so that interfacing could be easier. 

Would you have any suggestion on where i can find such an option.

[Altera_Forum]

Is there some way to connect conduit signals with avalon-mm slave ports. Can anyone shed some light on this. It would be greatly helpful.

[Altera_Forum]

Just enable the second port and export it. The Avalon-MM slave interface will be exposed out of your system.