Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Freeze wrapper error in Arria 10 Custom Platform Customization example



I was trying the Intel Arria 10 Custom Platform Customization Example from Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL* user guide (2018.10.30). I am using Quartus prime pro 17.1.2 version. 

After copying the files to the original custom platform directory, I was compiling my vector_add kernel to regenerate the new custom platform. I'm getting the following errors:

Error (18514): Child partition "freeze_wrapper_inst|kernel_system_inst" expects its parent to drive input port "kernel_sc_fifo_in_valid", but this port is not driven from its parent partition "|". Modify either the child or parent partitions so that all expected signals are correctly driven from the parent partition.

Error (18624): Partition "freeze_wrapper_inst|kernel_system_inst" contains output port "kernel_sc_fifo_out_valid" that is ignored by its parent partition "|". Consider modifying your design so that all output ports are connected to their parent partitions.

I am getting these two sets of errors on all the following ports that I added to the freeze wrapper. 

input [63:0] board_kernel_sc_fifo_in_data,
input board_kernel_sc_fifo_in_valid,
output board_kernel_sc_fifo_in_ready,
output [63:0] board_kernel_sc_fifo_out_data,
output board_kernel_sc_fifo_out_valid,
input board_kernel_sc_fifo_out_ready

While instantiating the kernel_system in freeze_wrapper, I have connected these ports to the corresponding ports of kernel_system. Therefore, kernel_system is actually being driven by its parent freeze_wrapper. 

Any help with debugging the issue will be highly appreciated. I have attached my log file here. 

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5 Replies

Hi ,

Please let us know any timing violation or other warning messages appeared after connecting the extra ports and Compiling / generating in Quartus.

Thanks and Regards



I have attached the generation warning and system messages for board.qsys and kernel_system.qsys after adding the new components. 

After adding the components, I compiled the Quartus project to debug any errors in my design. The compilation went successfully. The warnings are attached in the compilation_warning.txt file. 

Note: The error I mentioned in my post occurs in the fitter stage. I have tried another design by creating a bridge between kernel and flash memory. I faced the exact same error. 

Any help or pointer to solve the problem will be highly appreciated. 


Hi @Masudul_Quraishi,

Thank you for your patients, after some investigation on the warning as well as errors, we would suggest and try to look at the top level verilog files (i.e. top.v) and compare it with the connection between the freeze wrapper and board.qsys to see if any anomaly for connection is found.

Another perspective that we can try out is maybe better to try and build a flat flow to see if the design can be synthesized and check the RTL viewer for the connection. (most likely you will see some floating ports).

Warm regards.


Hi @Masudul_Quraishi,

By any chances did you managed to look into the suggest above to see if it works?

Warm regards.



Hi @Masudul_Quraishi,

Hope this message find you well and good day, as we do not receive any response from you to the previous clarification that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 
Warm Regards