Hello everyone,
I want to design a frequency counter, which function is to count the input signal's frequency.
And the result need to be write into memory for a specific period. ( I use "gate" to control.)
In the measurement result , there were also 2~ 3000 data that was unexpected. (total data number :393216), and I don't know what's wrong with my design.
It's the first time I know about the CDC issues and use the timing analyzer to check the timing issue, so I'm not really sure about what I do is correct or not.
Here shows my design's RTL plot:
And here is the timing analyzer's report:
The principle of frequency counter is count the cycle number of clk during the high level of fin,
and reset the value of counter when fin is at low level.
Beacuse I want the frequency counter's result become more intuitive, so I use a divider to divide the fin by 2,that means the counter will count the number of clk during one fin period.
And for the synchronizer, I use 2DFF synchronizer it to sync the fin signal to the clk domain.
Blue components in the plot is my frequency counter, and the frequency counter's output will goes into FIFO_1.
For FIFO_1, I want to use it to sustain the counter's value for one fin's clock, and because the frequency counter's output will be multiple bits value which is being trigger by clk, so I think I should use FIFO to let the counter's value cross to fin's domain.
And for FIFO_2, beacause I want to use gate (which is generated from clk) to control when the counter's value can write into memory, so I use second FIFO to let the counter's value (in fin domain) cross to the clk(gate) domain again.
I think I do my best to solve all the CDC problems, and the timing report shows no error.
So I don't have any idea why the measurement result still have unexpected value.
Can someone help me? Thanks.
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