Frequency division for use in an 8x1 multiplexer

[Altera_Forum]

Greetings everyone, I want to design an 8x1 Multiplexing system. Starting with a frequency of (50 MHz) as the first input to the multiplexer; I want to divide this frequency by (2,3,...,8). What can I do to accomplish this task???? I am also using Block Diagram Schematics and I am sorry because I know this section of the forum is reserved for (VHDL) only. I suppose the coding is also good, but a little more difficult. So please help me I don't know what to do with my project. Can I use 4 PLLs and give each one a different frequency??? Thanks for your help.

[Altera_Forum]

I suggest generating clock enables at the required frequency. Having multiple clock domains will be a real timing headache. Clock enables mean you keep the whole system using one clock, but only enabled once every 2/3/8 clocks etc.

[Altera_Forum]

Thank you indeed for your suggestion. But I'm afraid I'm using Block Diagram/Schematics for the project. Of course, I can add clk_enables to the counters, but then what?? Again I apologize for discussing non-VHDL matters here. Can I for example, manipulate with the VHDL code for the counter after I translate the blocks to VHDL?? Thanks again.

[Altera_Forum]

You can do in VHDL the same as the block diagram, and vice versa. So creating clock enables is a good idea. 

Yes you can modify the VHDL after you generate it from block diagram, but you must remember to remove the block from the project and add the VHDL to the project. You cannot covert VHDL to block diagram.