From Quartus VHDL code to ModelSim Simulation

[Altera_Forum]

Hello, 

please i have a very simple and basic application created in VHDL code that i want to implement in NIOS 2 processor and i would like to link it to ModelSim in order to simulate it. (it's a simple hello world application), thanks for any tips you can give me to help me understand all this. Thanks again! s

[Altera_Forum]

See AN 351, "Simulating Nios II Embedded Processor Designs", at http://www.altera.com/literature/lit-an.jsp. It was out of date when I last looked at it, but hopefully it is useable with its recent update.

[Altera_Forum]

First thanks for the answer. I've already tried the an 351 tutorial but unfortunately not every step is explained in this altera tutorial and i'm really a beginner. Actually right now i've already made some progress but still don't master the simulation with Modelsim of ip's related to the nios microproc and designed with the quartus 2 and nios ide(SOPC) tools. 

If you have any other clues that can help me i'll be grateful !

[Altera_Forum]

Hi, 

I followed the AN 351 tutorilal and this the error I had after clicking on "generate" in SOPC Builder Sytem Generation tab : Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\Applications\quartusII8.1\nios2eds\examples\vhdl\niosII_stratixII_2s60\standard\NiosII_stratixII_2s60_standard.sopc (Access denied) :confused:

[Altera_Forum]

Hi, 

I have a question if somebody can help me : is it necessary for a Quartus II project to be successfully compiled before simulating it or trying it on development board? Great thanks for patience to reply to such beginning questions:)

[Altera_Forum]

--- Quote Start ---  Hi, I have a question if somebody can help me : is it necessary for a Quartus II project to be successfully compiled before simulating it or trying it on development board? Great thanks for patience to reply to such beginning questions:)  --- Quote End ---    You may be lucky enough to give up simulation, chances may be better than winning a Euro lottery. As to compilation, you can't be serious, you can't give it up even if you are designing - with respect - for a flying carpet project.  Technically it is the compilation that produces the final firmware files to be downloaded into your chip. Quartus assembler wouldn't produce these files unless it successfully passes the compilation test.

[Altera_Forum]

--- Quote Start ---  is it necessary for a Quartus II project to be successfully compiled before simulating it or trying it on development board?  --- Quote End ---     As kaz mentioned, you must compile through the Assembler step to get programming files for your board.  You have to get through the Fitter and EDA Netlist Writer to do gate-level simulation, which is usually done as a timing simulation (uses timing information based on the actual fit).  For simulation at the HDL level you don't have to run Quartus at all if using a third-party tool. You have to run "Generate Functional Simulation Netlist" but do not have to run the Fitter if using the Quartus simulator.

[Altera_Forum]

Thank you for your response. Thanks to your help i made big progress and i'll soon be able to help those who have the same problem i had (specially while trying to simulate the very simple "hello world" example, Altera AN 351). 

 In fact now i'm able to add the IPs (with SOPC Builder), to generate the VHDL files, create and build the project with Nios IDE, and then running the simulation with modelsim by entering "s". Though i can't find the "hello world" phrase in the txd signal ( signal out of the UART according to documentation).   The error seem to be in the UART since the uart rxd signal is Undefined (in red in modelsim) and txd value has always "1" so i suspect the program is not processed (simulated actually) or there's a communication problem (nios - uart) or even the architecture i've designed with SOPC is malfunctionning. I've used 3 IPs : the cpu nios, the onchi memory and the UART.   Please any ideas? (this shoul be the final step ! )   thanks and read you soon

[Altera_Forum]

hi, 

i have done a verilog code and simulate using functional simulation mode in Quartus II version 9. but then, i simulated using model-sim altera. the problem is, i didn't get the same answer in modelsim compate to quartus although i'm giving the same input.   eg in quartus outputA=7520B (hex) but in modelsim outputA= 104505 (hex)   why is it so?  where is the problem actually? pelase anyone help me, thanks in advanced.