Gate Level Simulation

[Altera_Forum]

To run the simulation using the Quartus II (10.1) NativeLink feature, on the Tools menu, under EDA Simulation Tool, I clicked Run EDA Gate Level Simulation. 

Modelsim was invoked but the simulation result was RTL and not gate level simulation. The simulation appeared to be logical, without delays. What is missing?  What should be done to direct modelsim to gate level simulation?

[Altera_Forum]

Hi:  

 I myself use GL simualtion just now and with my limited experience, you should first check if you compile the design. If you did, check the "Generate netlist for functional simulation only" is off. You can find the option in Assignment - Setting - EDA Tool Settings - Simualtion - More EDA Netlist Writer Settings.   Good luck!