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Gate level simulation using Nc-verilog

Altera_Forum
Honored Contributor II
‎07-03-2008 04:43 AM
2,521 Views

Hello , 

I am facing problem when i tried to simulate netlist with SDO file . I generated  

netlist using quartus 2 7.2 version, stratix device. If do not include SDO file , it is simulatng , but when i include SDO file , the following error is reported : 

 

-- (delayfile 

| 

ncvlog: *e,expmpa (..//pwmtop_v.sdo,23|0): expecting the keyword 'module', 'macromodule' or 'primitive'[a.1]. 

(`include file: ..//pwmtop_v.sdo line 23, file) 

 

I have included Stratix_atoms.v also. It is compiling . 

 

Kindly help me. 

 

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