General Timequest Questions

[Altera_Forum]

Hello, 

  I am hoping someone can help to shed some light on my questions. I am interested in what exactly the constraints on maximum speeds for a general IO are.   I have a toy verilog file with 2 inputs, the clk and signal, with a single always block clocking this into a register.      module testfile(input clk, input mysignal); reg signalreg /* synthesis noprune */; reg signalreg2 /* synthesis noprune */; always@(posedge clk) begin signalreg <= mysignal; end always@(posedge clk) begin signalreg2 <= signalreg; end endmodule    ( for some reason i had to clock the register into another register for timequest to report any paths ? even with no prune on the first register? )    Along with this I have an SDC file with the following, create_clock -name main_clk_virt -period 1.8 create_clock -name main_clk -period 1.8 derive_clock_uncertainty set_input_delay -clock main_clk_virt -max 0 set_input_delay -clock main_clk_virt -min 0    So this should be a perfect clock with perfect data with no variation in timing external to the FPGA.   (1) I have no pin assignments and am allowing Quartus II to assign the pins automatically. Now if I incrementally reduce the period, then eventually the timing fails on at least one corner. With this toy example and a perfect clock/data to the fpga, if it passes timing, is this the absolute maximum that would be achievable on general IO pins? or is there other things that could be optimized to get it to run faster? or are there other physical constraints on the IO pins that would limit the maximum input  (besides the obvious omitted delays in the external routing and source ).   (2) This leads to a second question, which is related to a clock not coming in on a dedicated pin. If I explicitly assign the clk and mysignal to general io pins, it seems that the clk still gets routed to a global clock, but there is a lot more variance in delay for the path from the input to the global clock than if it was on a dedicated refclk pin, so harder to meet both setup and hold requirements ? Is this variability in the path to the global clock the reason you usually do not route a faster clock on general io pins, or is there some other reason as well ?     (3) Also, if I explicitly assign the clk to a non-clk input pin but then allow quartus to pick a pin for the signal, then compile a few times reducing the period in my SDC file until timing fails - With this example above, is this the best possible speed I can achieve if the fitter is left to route and place the pin how it wants, or is there other things that could be optimized manually?   I do understand that a transceiver is a better option for data at faster rates, but this is mostly curiosity and finding out what is going on.   Thanks for any help!