Generated Clocks using TimeQuest

[Altera_Forum]

I couldn't find a specific constraints area on the forum so I hope I'm in the right place. 

 I have two clocks that are generated by outputs of a counter.  The counter is clocked at 100MHz, and I take bit 1 as a 25MHz and bit 2 at a 12.5 MHz clock.  I am trying to tell the tools about these clocks.  I have no reference to these clocks in my qsf file. In the sdc file I put :  create_clock -period 10 -name CLOCK100M [get_ports {CLOCK100M}] create_clock -period 40 -name LCLK [get_ports {LCLK}]  create_generated_clock -divide_by 4 -source [get_ports {CLOCK100M}] -name CLOCK25M [get_registers {fpga_test_ports:fpga_test_ports1|sClockCounter[1]}] create_generated_clock -divide_by 8 -source [get_ports {CLOCK100M}] -name CLOCK12M [get_registers {fpga_test_ports:fpga_test_ports1|sClockCounter[2]}]   The problem is I then get the following error message:  Warning: Node: raw_data_capture:raw_data_capture1|sClockCounter[1] was determined to be a clock but was found without an associated clock assignment.  Warning: Node: raw_data_capture:raw_data_capture1|sClockCounter[2] was determined to be a clock but was found without an associated clock assignment.  I have looked through the online documentation but I can't find what I am missing.   Can anyone help?

[Altera_Forum]

Is there any reason why you are using a counter instead of a pll or clock enables? A counter isn't recommended for that purpose... 

Do you have any warnings before about the clocks CLOCK25M and CLOCK12M? If for one reason or another Timequest can't find the register you indicate, it won't create the clock.

[Altera_Forum]

I've found the problem. 

 I was using:  fpga_test_ports1|sClockCounter[1]  when I should have been using:  raw_data_capture1|sClockCounter[1]  So my constraints were correct, it was what I was constraining that was incorrect.  To answer the previous post this is a legacy design that I have been asked to make some changes to. The less I touch the better!