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Altera_Forum
Honored Contributor I
815 Views

Generated clock

Hello, 

 

i will create a generated clock and need your help. 

 

I have a counter (1 to 2500), which increments every rising edge of clk. Then i set enable to "1" for one clock cycle and set it again to "0" till i count again to 2500. 

My system frequency is clk = 50MHz. 

 

Counter module: 

 

input parameter : clk 

output parameter : enable 

 

How should my generated clock look like? Do i have to consider the duty cycle? 

 

Is this right? 

create_generated_clock -name {enable} -source [get_ports clk] -divide_by {5000} [get_pins {counter|clk}] 

 

 

Greetings
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4 Replies
Altera_Forum
Honored Contributor I
40 Views

This is an SDC question, not VHDL. 

 

Are you saying that this "enable" signal you are creating drives clock inputs elsewhere in the design? If not, you don't even need this constraint. Or are you saying that enable is being fed out of the FPGA device? 

 

50MHz/5000=10KHz. That doesn't match the description of your design. Why not divide by 2500?
Altera_Forum
Honored Contributor I
40 Views

So, i uploaded a picture i think the question will be more clear. 

 

U6 has a counter and triggers U3 and U4 every 50us. The outputs of U3 and U4 should reach U6 in 10 clockcycles. And i want to do a timing analysis. I read, that i need a generated clock and also insert multicycle paths. But dont know how to do it correct.
Altera_Forum
Honored Contributor I
40 Views

OK, this is pretty tricky. Is there a clock input to U4 or is just combinational logic? If it's just combinational, you should add a clock to it to guarantee your timing requirements. Or you should be feeding that enable signal into the clock input, not the enable input of U4. 

 

You don't need a generated clock constraint (unless you do change the enable to feed the clock input of U4), but like you said, you do need multicycle between U3/U4 and U6 if you are saying that it will always take up to 10 clock cycles for data to get to U6. 

 

For U3 to U6, you need something like this: 

 

set_multicycle_path -from {get_pins <output of U3>} -to {get_pins <input of U6>} -setup 10 

set_multicycle_path -from {get_pins <output of U3>} -to {get_pins <input of U6>} -hold 9 

 

This is "opening the window," extending the setup analysis to 10 cycles and adjusting the hold analysis to compensate.
Altera_Forum
Honored Contributor I
40 Views

there is no clock input in U4. It stores the ADC samples (sampling frequency 1MHz). Whenever i have a rising edge of enable (generated by U6), the outputs of U3 and U4 should be updated. 

So, when i use the enable as clock i need a generated clock constraint, right? Now, my enable signal is "0" till 2049 and "1" by 2500. How can i define it in my SDC file? Is it a proper way? 

 

To your suggestion with adding a clock: 

Just adding a clock to U4 and update the output whenever enable is set to "1"?
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