Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15311 Discussions

How do I connect 4, 4-bit, busses each to an LPM_MUX?

Honored Contributor I

I am trying to employ busses and LPM_MUX to simplify an ALU design. My wires are all replaced with bus wires, but I do not understand how to connect each of my 4 inputs to their corresponding input lines on the mux. The first input is /A, the second is A+B, and the last two are just placeholders until I can get the first two working.  


I have tried many different bracketing methods, but there are error messages saying I have width mismatches. Others say something like "node 'DATA3_3' does not have input." 


Similar issues are arising with the LPM_OR, but I suspect fixing one will fix both. (I am relatively new to Quartus, and I'm trying to teach myself how to use the busses and LPM functions.)
0 Kudos
1 Reply
Honored Contributor I


--- Quote Start ---  

(I am relatively new to Quartus, and I'm trying to teach myself how to use the busses and LPM functions.) 

--- Quote End ---  

That`s great. 

Here AHDL bus notation is used to create multiple pins so just give name( aabar[3..0],aorrslt[3..0],c[3..0],d[3..0])) to the wires by right click-> Properties. 

You can use lpm_inv & lpm_or Magafunctions as well, Check the screenshot for reference. 


Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 


Best Regards 

Vikas Jathar  

(This message was posted on behalf of Intel Corporation)