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Altera_Forum
Honored Contributor I
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Quartus Pro and post-synth QDB for IP cores: Covering more than a single FPGA

Hello, 

 

I'm looking for is a substitute for a post-synthesis netlist in Quartus Pro, for the purpose of delivering IP cores. The Standard Edition has the QXP format, which works reasonably well for this purpose, but is not supported by Quartus Pro. 

 

Following section 7.4 in the Pro Edition's Handbook Volume 1, I've successfully managed to generate a post-synthesis QDB in Quartus Pro, and deploy it in a target design. However Quartus Pro will not accept the QDB file in the target design unless the IP core has been compiled for exactly the same fpga part number

 

This means that if I deliver an IP core for Arria-10, the customer can't switch to another FPGA in the Arria-10 family without having me resynthesizing the IP core. There is no such problem with QXP files (let alone EDIF, which Quartus doesn't support). 

 

Attempting to compile a project with a QDB file that doesn't match the targeted part number exactly yields an error like 

 

Error(18097): Partition "|" contains assignment "DEVICE" with setting "10AX115S3F45E2SG", which is different from setting "10AX115S2F45I2VG" in partition "foo_ins|my_core_ins". Modify your design so all partitions use the same setting for the specified assignment. 

 

Is there a way to solve this? An QDB for a specific part number is pretty useless. Maybe allow the end users to change the target part number of the QDB somehow? Or a way to generate an QDB that covers an entire device family? 

 

Or maybe the QDB format isn't the way to go at all? But if so, what is? Encrypted sources is not an option. 

 

Software used: Quartus Prime Version 17.1.0 Build 240 SJ Pro Edition running on a Linux machine. 

 

Thanks in advance, 

Eli
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10 Replies
Altera_Forum
Honored Contributor I
256 Views

When you generated the .qdb file in the developer project, are you sure you selected the "synthesized" snapshot? Using any other Fitter snapshot would cause the issue you mention. See slide 17 in this training: 

 

https://www.altera.com/support/training/course/obbdr100.html
Altera_Forum
Honored Contributor I
256 Views

Hello, 

 

Yes, I'm positive that it was the synthesized snapshot. For one, because I never ran the fitter on the design I exported from (it's not something you can do accidentally, given the time it takes to complete on Arria-10). And also because I did this directly with the command line: 

 

quartus_cdb my_core -c my_core --export_partition my_core --snapshot synthesized --file my_core.qdb 

 

So there's no doubt about that. 

 

Regards, 

Eli
Altera_Forum
Honored Contributor I
256 Views

Hmm, that is very strange. Is my_core the top-level or a lower level partition? If it's the top-level, that may be the problem.

Altera_Forum
Honored Contributor I
256 Views

It was not the top-level partition. I was aware that the root partition should not be exported when I did this.

Altera_Forum
Honored Contributor I
256 Views

Oof. Well then I'm not sure what is going on! I guess you could try trashing the project's qdb folder, resynthesize the design and try again. Very strange.

Altera_Forum
Honored Contributor I
256 Views

Been there, done that. A few times. :) 

 

I saw that a different FPGA should be targetable with post-synthesis snapshots in the online course you referred to. 

 

However the Handbook [1] actually says the opposite, more or less. Section 7.4.1.4 of the Handbook [1] goes: "Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device part number and use the same Intel Quartus Prime version as the Developer project." 

 

The examples around this section imply that it talks about post-fitting or finalized snapshots, but I didn't see any distinction between synthesized snapshot and the other variants in the text itself. And the part requiring the same Quartus version isn't all that encouraging. 

 

So it's not clear where this stands. 

 

Regards, 

Eli 

 

[1] Intel Quartus Prime Pro Edition Handbook Volume 1: Design and Compilation, 2017.11.06 (qts-qpp-handbook.pdf)
Altera_Forum
Honored Contributor I
256 Views

Well, I just checked it out and the handbook is correct. The training is wrong. The devices have to match.

Altera_Forum
Honored Contributor I
256 Views

Thank you. 

 

That brings me back to the original question: How can I deliver an IP core in a format that works as well as a netlist, for use with Quartus Pro? 

 

Regards, 

Eli
Altera_Forum
Honored Contributor I
256 Views

 

--- Quote Start ---  

Thank you. 

 

That brings me back to the original question: How can I deliver an IP core in a format that works as well as a netlist, for use with Quartus Pro? 

 

Regards, 

Eli 

--- Quote End ---  

 

I am interested in the answer to this as well. I see the same problem in Quartus 17.1 Pro.
Altera_Forum
Honored Contributor I
256 Views

Hi, 

 

The solution might be Quartus' VQM netlist format, which I've opened a separate thread about: 

 

https://www.alteraforum.com/forum/showthread.php?t=59212 

 

Those interested in this topic might be interested looking there as well. 

 

Regards, 

Eli
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