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QVM netlist generated by Quartus: Safe for use?

Honored Contributor II



Quite a few months after my yet unsolved thread ( on how to generate an IP core netlist for delivery on Quartus Pro, it struck me that maybe the VQM format can be used instead. Actually, maybe VQM should have been used all along. This is the format that third-party synthesizers (e.g. Synplify Pro) use to convey their netlist to Quartus. It's essentially a Verilog file describing the netlist (instead of an EDIF, but with the same low-level touch). 


It also turns out that Quartus own toolchain can generate a VQM with 


$ quartus_cdb my_core --vqm=my_core.vqm 

Adopting this file into a design merely consists of adding a line like this to the QSF file: 


set_global_assignment -name VQM_FILE /path/to/my_core.vqm 

or adding the QVM file with the GUI. This is mainstream thing in Quartus. 


But there's a catch. The two first lines of the VQM file generated by Quartus read as follows: 


// !!!!!! This generated VQM is intended for Academic use or Internal Altera use only !!!!!! // Functionality may not be correct on the programmed device or in simulation 

However my own experiments with using the VQM file instead of QXP show it works like a charm. Actually, anecdotal experiments show that it's easier to meet timing when the core was adopted as a VQM, compared with QXP. I don't know if this is encouraging or discouraging (that there's a difference), or just plain chance. 


So: Does anyone have additional information on how safe (or unsafe) it is to use these Quartus-generated VQM netlists? Is there any reason for this exclamation marks warning, or is it just because nobody has cared about this feature so far? 


This is important: The VQM netlist format could be the solution for many Quartus Standard / Quartus Pro incompatibility headaches. Given that it's safe to work with, of course. 


Thanks in advance, 

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