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Generation of buffer when taking port as "inout"

Altera_Forum
Honored Contributor II
‎02-22-2010 08:07 AM
1,467 Views

Hi, 

I have make simple program as below where a is "input" port,b is "output" port and x is "wire". 

buf b1(x,a); 

buf b2(b,x); 

Here if i take b as "inout" port it is generating one extra buffer in RTL view.What is the reason?
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Altera_Forum
Honored Contributor II
‎02-22-2010 10:02 AM
664 Views

Examine the technology map to see the real FPGA implementation.

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