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Altera_Forum
Honored Contributor I
867 Views

Getting Quartus to recognize a Recirculation Mux Synchronizer

Hi all, 

 

I'm attempting to perform a CDC of a Data bus that switches values with a Write Strobe using a "Recirculation Mux Synchronizer". In essence the Write Strobe is synchronized across the Async clocks and the synchronized pulse is then used as an enable on the Data bus latching clock (similar to what is shown in the attached image). 

 

The https://alteraforum.com/forum/attachment.php?attachmentid=15789&stc=1 "Managing Metastability with the Intel Quartus Prime Software" section of the Quartus Handbook, the tool has the capability to recognize a Synchronization Register Chain. As such, I would expect the tool to ignore timing this path, but that's not whats happening. Since the Data latching flop uses an enable that is synchronized to the latch clock, shouldn't the entire path be ignored if the tool recognizes the synchronization register chain? Am I misunderstanding this? 

 

If not, then is there a way to make Quartus recognize this as an Async path without setting Async clock groups, false paths or multicycle paths? This is for IP that will be instantiated inside a top level design and I was hoping to set individual exceptions across nodes. 

 

Thanks for your help!
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2 Replies
Altera_Forum
Honored Contributor I
113 Views

 

--- Quote Start ---  

Hi all, 

 

I'm attempting to perform a CDC of a Data bus that switches values with a Write Strobe using a "Recirculation Mux Synchronizer". In essence the Write Strobe is synchronized across the Async clocks and the synchronized pulse is then used as an enable on the Data bus latching clock (similar to what is shown in the attached image). 

 

The https://alteraforum.com/forum/attachment.php?attachmentid=15789&stc=1 "Managing Metastability with the Intel Quartus Prime Software" section of the Quartus Handbook, the tool has the capability to recognize a Synchronization Register Chain. As such, I would expect the tool to ignore timing this path, but that's not whats happening. Since the Data latching flop uses an enable that is synchronized to the latch clock, shouldn't the entire path be ignored if the tool recognizes the synchronization register chain? Am I misunderstanding this? 

 

If not, then is there a way to make Quartus recognize this as an Async path without setting Async clock groups, false paths or multicycle paths? This is for IP that will be instantiated inside a top level design and I was hoping to set individual exceptions across nodes. 

 

Thanks for your help! 

--- Quote End ---  

 

 

My observation is that Quartus can be set to recognise synchroniser chains but the user must enter timing constraints, a bit pointless
Altera_Forum
Honored Contributor I
113 Views

 

--- Quote Start ---  

My observation is that Quartus can be set to recognise synchroniser chains but the user must enter timing constraints, a bit pointless 

--- Quote End ---  

 

 

Indeed! I suppose the Synchronizer recognition is really only used for the Metastability Analysis portion. I had a feeling that was the case, but your answer solidified it. Not sure why Altera (Intel) can't just ignore that path if the tool already recognizes is as such though. Hopefully this is something that can be supported in the near future. 

 

Thanks for your help!
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