module test (clk,led);
reg [7:0] counter;
always@(posedge clk) begin
if (counter < 100) counter <= counter +1;
else counter <= 0;
always @ (counter) begin
if (counter>0) led = 1;
else if (counter<20) led = 1;
else led = 0;
trying to make sure that the value of led turns 1 only when the value of counter varies from 1 to 20. I want led to be zero when counter is zero. any workaround this or am i doing something wrong?
You need to declare 'led' as a reg, in the same way you've declared counter. Declaring it as an output to the module isn't enough (as it is in other languages).
You can either add:
or change the output declaration to:
output reg led;
For more complete information about compiler optimizations, see our Optimization Notice.