Guidance on SPI Interface Stratix III with ADC DAC Loopback in Verilog

[Altera_Forum]

I have basic Verilog fundamentals from undergrad with Xilinx and the Nexys2 Spartan-3E board. I'm currently new into Altera Quartus II software (did the tutorials) and working with the Stratix III EP3SL150F1152 DSP Developers Kit. I'm currently working on a custom board with an ADC 14-bit ISLA214P50 (500MSPS), 16-bit DAC5681 (1GSPS) and a CDCM7005 that is supposed to communicate with the FPGA via HSMC. My questions are: 1) How about would you implement SPI with the FPGA as the master and the others as slaves in Verilog? Even a starter link/example would do since I've never done this in Verilog before. I just need any guidance, not the answer. 2) How can I verify this would work when I have ADC in, DAC out via UART (besides SignalTap and verifying on scope)?

[Altera_Forum]

A quick search for "verilog spi module" returns plenty of links that should help. If you have some basic verilog understanding you should be able to fathom some of what's there. You might want to start by looking through this example (https://github.com/zouppen/simulavr/blob/master/examples/verilog/spi.v). Equally useful is this link (http://www.elecdude.com/2013/10/spi-verilog-code-master-slave-code-with.html). Note: these are both somewhat idealistic implementations and wouldn't be how I would implement an SPI interface for a real application. However, they should prove very useful exercises. 

 As for verification - you don't list simulation. Essential, long before you get to SignalTap or an oscilloscope. The link above has a suitable test harness included.  Cheers, Alex