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HDL OPenCL issues (Avalon ST Interface Issues)

Altera_Forum
Honored Contributor II
811 Views

Hi, 

Please can someone did work with HDL and OpenCL (Avalon ST interface). 

I did a very simple project with HDL-kernel Co-design like the first advanced example in altera design examples. And my question is about valid and ready signal in Avalon interface ? I force valid signal to 0. When valid signal is 0 it suppose no valid data is being to be transfered. 

What I did, I tried to print with printf fonction the data transfered from HDL module to kernel when valid is 0 and the problem I have exactly the same data transfered.  

My data is always transfered from HDL to Kernel and it doesn't matter when valid signal is 0 (invalid data) or 1 (valid data) !!! 

I don't know how to fix it ? What happens with Avalon interface when valid Signal is 0 ? 

Thank you.
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1 Reply
Altera_Forum
Honored Contributor II
79 Views

I am not an expert on mixing HDL with OpenCL or the Avalon interface, however, valid signals usually work in this way that data is still transferred whether the valid signal is set or reset, and the circuit on the receiving side must decide what to with invalid data.

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