HDL Testbench in ModelSim Altera Edition

[Altera_Forum]

I have been a Xilinx user in the past and I'm currently moving a design from a Xilinx part to an Altera part and having some issues with simulation. I have a VHDL testbench that runs flawlessly in the Xilinx tool chain but I am finding the method that Quartus II handles simulation is significantly less intuitive. In Xilinx ISE the testbench can be defined as the top level file and you can simply run simulations from this, not the case with Quatrus II / ModelSim Altera Edition. 

 My testbench has a top level file that instantiates the FPGA design and also a driver module that reads data from a text file and generates signals for the design under test, the exact inputs from the testbench depend on some of the outputs from the design (i.e. the design signals reset and testbench stops stimulus into the design).  Are there any decent resources or training modules on porting a simulation modules that are fully defined in HDL to the required inputs for for the Altera environment (e.g. vector waveform files)?

[Altera_Forum]

you are mis-judging your problem. same rules of testbench applies to quartus as xilinx (or rather say modelsim). are you talking about modelsim? or synthesis

[Altera_Forum]

I am trying to simulate through modelsim using a testbench that is currently run using Xilinx ISE by setting it as the top level module and running the simulation.  

 Initially I did the same thing in Quartus II and attempted RTL simulation and generated errors, my understanding is Quartus II does not support simulation in the same fashion as Xilinx ISE and that additional steps in ModelSim Altera Edition are required. If available I was looking for guidance on moving designs from Xilinx to Altera.  For example, if I had a simple counter and instantiated it in a top level testbench file along with the following process the Xinlinx ISE will simulate the counter, my understanding is Quatrus II requires a more steps in the simulation flow and wanted to see if there was decent documentation on changing over.  process(CLK) begin   clk <= not clk after 20 ns; end process

[Altera_Forum]

Quartus synthesis tool does not support simulation. If you mean modelsim then your counter should work irrespective of synthesis tool. 

When in modelsim, the tool doesn't care about your synthesis tool and doesn't want to know it.

[Altera_Forum]

Some confusion about what is Quartus and what is ModelSim may be a result of Quartus NativeLink, and getting Quartus to generate testbench templates and launch Modelsim simulations etc. etc.

[Altera_Forum]

Thanks for the prompt responses. I'm aware Quartus II does not support simulation and that I need work through ModelSim. I am running ModelSim Altera Starter Edition 10.3c but not seeing exactly how a testbench and associated FPGA design would be simply simulated in a similar fashion as I have been doing so in Xilinx ISE, clearly other steps to get to a working simulation are required. 

 I have not heard of NativeLink before, but it loos like it may help me. I plan on working through this example: https://www.altera.com/support/support-resources/design-examples/design-software/simulation/modelsim/exm-ncsim-native-link.html  Are there any other good resources to understand how best to move designs from Xilinx's tool chain to Altera's? Altera application note AN307 looks like it may be of some help but does not seam to cover running existing testbenchs through Altera's tool chain.

[Altera_Forum]

Modelsim is a universal simulator - you can simulate code for any system. 

I suggest pulling out the user guide and learning how to use it in command line mode - its quite straight forward and can be scripted for larger runs.  In the command line:   cd <your working directory> # make the work library vlib work # compile all the files vcom file1.vhdl vcom file2.vhdl # or if you have verilog vlog file3.v # now start a simulation vsim my_top_level # run it for some time run 1 us # start simulation over restart -f   for other libraries, you can use vlib <libraryname> to create them for already compiled libraries (in modelsim)  vmap <library_name> <path to library>  This is the base for all simulations. It will do you well to learn it.

[Altera_Forum]

--- Quote Start ---  Thanks for the prompt responses. I'm aware Quartus II does not support simulation and that I need work through ModelSim. I am running ModelSim Altera Starter Edition 10.3c but not seeing exactly how a testbench and associated FPGA design would be simply simulated in a similar fashion as I have been doing so in Xilinx ISE, clearly other steps to get to a working simulation are required.  --- Quote End ---    You're used to the Xilinx tools' integration of the simulation tool into the entire suite. Altera (and the other guys, too) doesn't do that. (Well, there's Native Link but ignore it for the moment.)  I'm pretty sure that there are simple ModelSim tutorials online somewhere. But anyways: Start ModelSim AE standalone. Create a new project (File | New ... Project). Put the project somewhere. It'll ask you if you want to create a new file, or add an existing file, and create a simulation. Click "close."  You'll see a window with the title "Project - "E:/Path/To/My/Project" on the top, and it'll have two tabs, "Library'" and "Project." Since the project is new, the Project tab is empty. Right-click in there and choose "add to project." options include "new file," "existing file," and others. If you've got sources you want to simulate, choose "existing file." Mouse around to your files.  At some point you will have added all of your sources, including the test bench, and it will be time to simulate. first, ensure that all of the files are in the correct compilation order: right-click in the project area, choose Compile, then Compile order.  Then compile everything.  Finally. create a simulation configuration: right-click then Add to Project then Simulation Configuration. give it a name. In the "design" tab, look for the "work" library. Click the + to expand it. Look for the entity corresponding to your test bench. Click its + to expand, and select the test bench architecture. Click save.  to run the simulation, doubleclick on the simulation configuration. Watch the transcript window, you'll see messages and such. When it's done, you should see a list of instances, objects and processes, as well as a WAVE window. (If you don't see the wave window, choose View -> Wave from the main menu. to add signals to the wave view, click on the instances you see in the sim view. You might need to click a + or two to expand. Then select signals in the Objects window. Click and drag to the wave view, or right-click and choose "add to wave."  run the simulation by typing   VSIM 3> run 1000 us  in the transcript window. The VSIM 3> is a prompt. You can make the time anything you wish.  Save the list of signals in the wave view by clicking in the wave view, then choosing File -> Save Format .. from the main menu. Give the file a name. (The .do extension means that it is saved as a macro, which is the standard thing.)  To restart a simulation if you need to recompile sources, choose Simulate -> End Simulation from the main menu. Rerun the simulation by doubleclicking on the simulation configuration. Reload your saved signals into the wave view by typing:  VSIM 10>do wave.do   or whatever you called the waveform list macro file.  good luck.

[Altera_Forum]

--- Quote Start ---   (Well, there's Native Link but ignore it for the moment.)  --- Quote End ---    .... and not ignoring NativeLink, here the high level flow of what you do:  1) write your FPGA top-level as you normally would for synthesis.  2) either write your testbench from scratch, or after it successfully compiles you can use within Quartus menu Processing->Start->Start Test Bench Template Writer. All this is going to do for you is inspect your toplevel and generate a blank VHDL testbench file that instantiates your toplevel and provides signals with correct names. It's useful if you're starting from scratch, but it's entirely possible your ISE VHDL test benches just may need minor edits?  3) write the VHDL to apply the behavior you want applied for your testbench  4) configure NativeLink to run your testbench. Assignments->Settings->EDA Tool Settings->Simulation. In the bottom section related to NativeLink, select the "Compile Test Bench" radio button and then click on Test Benches... and New.... and fill out the dialog box with information about your testbench.  5) within Quartus, click Tools->Run Simulation Tool->RTL Simulation. This will launch Modelsim, compile the simulation files, add the top-level signals to the waveform, and run your simulation.   Steps 1-4 are one-time tasks, while (5) you can do for the life of your project. The (small?) benefit that NativeLink adds is that as your FPGA project contents grow, Quartus will update the Modelsim scripts so you can somewhat eliminate duplication of effort in maintaining Quartus and Modelsim projects.  Attached is a trivial Quartus project with a single register and a testbench created using the template writer and then customized to add the CLK, ACLR, D input generation. Open the .qar in Quartus, compile the project, and then launch the RTL Simulation to see it run.  I think if the original poster follows up with a description/example of how XIlinx does things and the shortcomings with the Altera approach, then others can probably suggest relatively simple alternatives.

[Altera_Forum]

Thanks for the above feedback and the sample project, everyone has been quite helpful here.  

 After some more work I've gotten the testbench and FPGA implementation that run through Xilinx ISE to run with the same results in Modelsim AE, with some modifications (substitutions of Xilinx specific IDDR2 blocks and some differences between what environments allow).  As you mentioned above I'm used to Xilinx's tools, the simulation integration in ISE really streamlines the whole process but allows the user to pretty much ignore the inner workings of ModelSim. I think I'll be spending some time reviewing the ModelSim user guide.

[Altera_Forum]

Modelsim (now questa) has many more features that ISIM does not have (code coverage, profiling), and has much better language support (SV, VHDL2008). But you have to pay for it.