HPC II DDR controller performance

[Altera_Forum]

I have the controller integrated and working and now just trying to optimize performance. 

Using HPC II, Full "Controller data rate" with half rate bridge.  The read/write behavior is write data to consecutive addresses (~200 writes) followed by read data from consecutive addresses (~200 reads). And continuing to alternate between write and read sequences indefinitely.  For some sequences, the writes are interrupted say half way through by almost 30 local clock cycles of mast_ready = '0' thus holding off further writes.  For some write sequences, 200 writes can go through without interruption.  I am trying to understand what specifically causes this and looking for ways to minimize the number of pause cycles(due to mast_ready='0').  More specific numbers.... From start of write sequence to end is 205 cycles. Paused cycles (due to mast_ready='0') are 34 (occurs in 3 groups of 4, 10, 20 cyc). This gives me 83.4% efficiency. And I am looking for more.  For now, I really only need maybe 10 minimum of these pause cycles removed for eff = 88.3 % to meet system requirements but high as possible is naturally better.  Using Quartus 9.1. Custom hardware.  Possibly some of the configuration options for the controller could be adjusted?  The memory preset settings could be a little off from the datasheet but would this be relevant - trying to understand what "buttons to push" to improve things.   Thanks all,  Cos.

[Altera_Forum]

Still no comments... 

 I myself put the "memory preset settings" as per the memory datasheet. Rebuilt and saw no noticeable difference. They were not that far off.  I myself made an adjustment to the controller config which was just changing the  look ahead queue depth to 8 (was 4). Rebuilt and saw no noticeable difference.  My local logic is not using bursts but not sure that that matters in this case. The mast_write is always high(cycle to cycle) unless mast_ready goes low. Again, no issues in some sequences of ~200 writes.  Still trying to understand the root cause of mast_ready being low for  so many cycles. If I knew that then I could target a change towards that. Would bursts make a difference? HPC II controller is somewhat of a black box.  It would be good for me to understand what kind of performance  I should be seeing.  Hope to see some replies on this.  Thx, -Cos

[Altera_Forum]

Not feeling the love. :( 

 It would be good to get some feedback. Gotta be some Altera folk out there who know something - eh? Or who can follow up and find out?  -Cos

[Altera_Forum]

This sounds similar to something I saw a year or two ago. It only happened with the HP2 controller and not the HP1 version (altmemphy I think). If I remember correctly the bug was that the command queue wasn't deep enough to keep up with the fill rate from my masters. Try switching to the HP1 controller to see if that solves the throughput problem. If that does the trick then you would have to upgrade your tools in order to use the HP2 controller. I can't remember when this was fixed but my guess is 10.0 or 10.1 resolved it (it's fixed I just can't remember when it happened).