Hard DDR3 Controller Fitting Problem on Cyclone V

[Altera_Forum]

Hi 

I have generated the DDR3 controller IP from IP Catalogue, using Quartus Prime v15.1; It generated an example design project too. After I assign my DDR3 pins to the FPGA pins & run the "..._pin_assignments.tcl" after Analysis & Synthesis, I try to implement the project. Unfortunately the Fitter fails and issues the following error:     --- Quote Start ---  Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HPHY(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Altera Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.  Error (175001): The Fitter cannot place 1 HPHY, which is within Altera DDR3 SDRAM External Memory Interface Example Design ip_ddr3_controller_example.  Info (14596): Information about the failing component(s):  Info (175028): The HPHY name(s):   ip_ddr3_controller_example_if0:if0|ip_ddr3_controller_example_if0_p0:p0|ip_ddr3_controller_example_if0_p0_acv_hard_memphy:umemphy|hphy_inst  Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:  Error (175006): Could not find path between the HPHY and destination pin  Info (175027): Destination: pin mem_a[13]  Info (175015): The I/O pad mem_a[13] is constrained to the location PIN_G6 due to: User Location Constraints (PIN_G6)  Info (14709): The constrained I/O pad is contained within this pin  Error (175022): The HPHY could not be placed in any location to satisfy its connectivity requirements  Info (175021): The pin was placed in location G6  Info (175029): 1 location affected  Info (175029): MEMPHY_X11_Y45_N1 Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.   --- Quote End ---    I searched the forum and the Altera knowledge-base, yet got no useful result. There are many posts similar to this, but none have been replied successfully.  I would be grateful if someone could help working it around. Thanks

[Altera_Forum]

I had a similar problem placing an LPDDR2 controller. In my case the package I chose (U484) would not support a X32 data width. I had to move to a F484 package. This was not obvious from the error messages.

[Altera_Forum]

Thanks gj_leeson 

 My FPGA part is 5CEFA4F23. What was your FPGA part? This could help me understand if I am verifying everything correctly. Also I could verify if my problem is the same.  Actually this is somewhat strange to me. In the "External Memory Interface Handbook" on Table 1-7 the only Cyclone V parts which could support DDR3 controller are the following: 5CGTD9, 5CEA9, 5CGXC9, 5CEA7, 5CGTD7, 5CGXC7 My part (5CEFA4F23 with 484 pins) has not been listed there!  On the other hand on "Cyclone V Product Table" and "Cyclone V Device Overview" all parts of 5CE category support DDR3 Controllers!!!!  How did you identify the root of your problem?  Thank you

[Altera_Forum]

I looked at "External Memory Interface Handbook" and in Table 6-5 it has been noted that A4 with F484 package supports X16 mode on the top side (my case); So this should not be my problem. 

BUT: When I changed the mem_a[13] (the failing node in the Fitter report) to pin C8 instead of G6 the Fitter succeeds. My problem is resolved this way, but WHY???? It is difficult to change PCB, so it would be beneficial if I could figure out the problem and resolve it inside the FPGA.  Thanks

[Altera_Forum]

I'm (now) using a 5CEFA5F23. I found the problem in a very circuitous way, but finally let the compiler choose the device and the pinout and it compiled successfully. This led me to look at the package options and finally the document that described the various limitations. Your problem sounds different and unfortunately I can't shed any light. I learned long ago, however, to make sure the compiler is happy with the device selection and pinout before committing to a PCB.

[Altera_Forum]

According to Altera Cyclone V pin-out file, the HMC pins are fixed and the address_bus[13] MUST be tied to C8 (for my device part number), so this is the problem & should be corrected. 

Thanks gj_leeson.

[Altera_Forum]

No problem, I'm glad you got to the bottom of it.