Having problems test benching with Model Sim from Quartus, any ideas?

Altera_Forum · ‎02-08-2016

// This is the test bench

`timescale 1 ps/ 1 ps

module sum_fix (valor_a,valor_b,result_fx,select);

input [7:-8] valor_a,valor_b;

output reg [8:-8] result_fx;

input select;

always@ (valor_a or valor_b)

begin

if (select==1)

result_fx = valor_a + valor_b;

else

result_fx = valor_a - valor_b;

end

endmodule

//This is the UUT

`timescale 1 ps/ 1 ps

module sum_fix_vlg_tst();

reg select;

reg [7:-8] valor_a;

reg [7:-8] valor_b;

// wires

wire [8:-8] result_fx;

sum_fix i1 (

.result_fx(result_fx),

.select(select),

.valor_a(valor_a),

.valor_b(valor_b)

);

initial

$monitor ("valor_a = %b, valor_b = %b, result_fx = %b", valor_a, valor_b, result_fx);

initial

begin # 10

select = 1;

valor_a = 32'b0000000011111111;

valor_b = 32'b0000000011111111;

# 20

valor_a = 32'b1111111111111111;

valor_b = 32'b1111111111111111;

# 30

valor_a = 32'b1001100111001000;

valor_b = 32'b0001111000111101;

end

endmodule

Compiled in Quartus well. Then I launch Modelsim like this: tools > rtl simulation. It launch Modelsim but it only gives me a lot of zzzzzzzzzzzzz in input and xxxxxxxxxxxxxx in output without anything in the wave.

I want to say that I'm not sure if I added this testbench correctly to the project. I'm a beginer. What I did was: assignments > settings > compile test: click test benches > new, looked for the file and add, and ok. I'm not sure that this is the correct way, because it looks too complex. Please help on this.

Also, I comment that I initiate the test bench writter template in quartus, but I ended changing everything from the file, final result is the code above.

Altera_Forum · ‎02-09-2016

It was checked in edaplayground, and code is perfect. I might be doing something wrong with quartus-modelsim

http://www.edaplayground.com/x/cyc

Altera_Forum · ‎02-09-2016

# Reading C:/altera/15.0/modelsim_ase/tcl/vsim/pref.tcl# do sum_fix_run_msim_rtl_verilog.do# if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Model Technology ModelSim PE vmap 10.3d Lib Mapping Utility 2014.10 Oct 7 2014# vmap -modelsim_quiet work rtl_work # Copying C:/altera/15.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied C:/altera/15.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vlog -vlog01compat -work work +incdir+C:/altera/15.0/PROYECTOS/Oper_fixed {C:/altera/15.0/PROYECTOS/Oper_fixed/sum_fix.v}# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 12:07:41 on Feb 09,2016# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/altera/15.0/PROYECTOS/Oper_fixed" C:/altera/15.0/PROYECTOS/Oper_fixed/sum_fix.v # -- Compiling module sum_fix# # Top level modules:# sum_fix# End time: 12:07:41 on Feb 09,2016, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# # vlog -vlog01compat -work work +incdir+C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim {C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim/sum_fix_tb.vt}# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 12:07:41 on Feb 09,2016# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim" C:/altera/15.0/PROYECTOS/Oper_fixed/simulation/modelsim/sum_fix_tb.vt # -- Compiling module sum_fix_vlg_tst# # Top level modules:# sum_fix_vlg_tst# End time: 12:07:41 on Feb 09,2016, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" sum_fix_tb.vt# # add wave *# view structure# view signals# .main_pane.objects.interior.cs.body.tree# run -all# ** Error: No Design Loaded!# Error in macro ./sum_fix_run_msim_rtl_verilog.do line 17# No Design Loaded!# while executing# "run -all"

Altera_Forum · ‎02-09-2016

I already fixed it, problem is that module name has to be the same that the file name, same than testbench file name in setting files. I have to say the whole proceed of Quartus Test bench is horrible, Xilinx is much more intuitive.

For example, since I have started learning Quartus-modelsim, I have to constantly launch and close, launch and close, otherwise I receive the message "error deleting "misim_transcript" ,permission denied. Check the Nativelink log file, C:/altera/15.0/....for detailed error message.

I wish to know if this is normal, or is it me that I'm handling the software correctly.