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The clock is being implemented using the seven segment display on the fpga in a 24 hour format. I need to be able to set the hours and minutes and this is what im struggling with. Im also struggling with the alarm function. It wont let me attach the verilog file, so I will just post my code below.
▪ Switch functions
o SW0=1 will act as a reset. Both the time and the alarm time should be reset to zero if
SW0 goes active. SW0 has priority over any other switch
o SW1 is the time_set switch, if it is set to 1 you are setting the time
o SW2 is the alarm_set switch, if it is set to 1 you are setting the alarm
o SW3=1 set hours, SW3=0 set minutes
o SW4=1 run the clock time
o SW5=1 active the alarm
▪ Push button functions
o KEY0 pressed (=0) causes the alarm to reset
o KEY1 pressed (=0) sets what ever is selected, let up it stops, you want the numbers changing at a 2Hz clock rate (twice a second)
definitions of these variables
clk_2Hz --- 2Hz clock
hrs1_min0 --- set hrs set to 1 to set minutes set to 0, SW3
reset --- resets the entire clock, SW0
t_set --- set clock time, SW1
a_set --- alarm time, SW2
run_clock --- run_clock = 1 would cause the clock to run, SW4
a_act- ? --- activates the alarm, SW5
almreset --- the alarm is going off and you want to reset it, KEY0
runset- ---- when this is 1 run, when this is 0 set
sec, min, hrs --- clock time
min_alarm, hrs_alarm --- alarm time
alrm --- the alarm
My code:
// Alarm Clock
//Clock Module
module ClockCounter(input clk_2Hz, run_clock, reset, input [7:0] MaxCount,
output reg [7:0] Count, output reg Carry);
always_ff@(posedge clk_2hz or posedge reset) begin
if (reset) begin
Count <= 0;
Carry <= 0;
end
else
if (run_clock)
if (Count < MaxCount) begin
Count <= Count + 8'd1;
Carry <= 0;
end
else begin
Count <= 0;
Carry <= 1;
end
end
endmodule
// Clock Timer
module timer(input clk_2Hz, reset_t, run_clock_t, t_set output [7:0] hrs, min, sec);
wire clk_sec, Carry_scl, Carry_mcl, Carry_hcl;
wire [7:0] fiftynine, twentythree;
assign clk_sec = clk_2Hz;
// Default constant values which will be max count for hours and minutes
assign fiftynine = 59;
assign twentythree = 23;
//Instantiation of clock counter module 3 times for hours,minutes and seconds clock
ClockCounter SecClk (clk_sec, run_clock_t, reset_t, fiftynine, sec, Carry_scl);
ClockCounter MinClk (Carry_scl, (run_clock_t|t_set), reset_t, fiftynine, min, Carry_mcl);
ClockCounter HrClk (Carry_mcl, (run_clock_t|t_set), reset_t, twentythree, hrs, Carry_hcl);
endmodule
// Alarm module
module alarm(input a_set, a_act, almreset, output reg [7:0] min_alrm, hrs_alrm, output reg alrm);
- Tags:
- systemverilog
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