HelloWorld - compiler error, not able to generate hardware

[Altera_Forum]

Hello, 

 Recently I bought the DE1-SoC Board for trying OpenCL with it. - I set up the environment variables like suggested in the "DE1SOC_OPENCL.pdf" - I have a valid licence. - I have downloaded the BSP for the Board  After trying to compile a .cl -File (the vector_add example from the intel site) with the command: aoc device/vector_add.cl -o bin/vector_add.aocx --report --board de1soc_sharedonly  I get the error: Compiler Error, not able to generate hardware. The .log file gave me following error-text:  ... info (21057): implemented 12069 device resources after synthesis - the final resource count might be different  info (21058): implemented 13 input pins  info (21059): implemented 45 output pins  info (21060): implemented 57 bidirectional pins  info (21061): implemented 10410 logic cells  info (21064): implemented 1528 ram segments  info (21065): implemented 1 plls  info (21071): implemented 1 partitions info: quartus prime analysis & synthesis was successful. 0 errors, 65 warnings  info: peak virtual memory: 1136 megabytes  info: processing ended: mon may 15 07:23:33 2017  info: elapsed time: 00:00:32  info: total cpu time (on all processors): 00:00:31 error (281039): finished parallel synthesis of 1 partition(s). 1 partitions did not finish parallel synthesis because there were errors  error (281040): partition "system_acl_iface_hps_hps_io_border:border" did not complete synthesis due to errors info (144001): generated suppressed messages file /home/developer/workspace/opencl_intel_tutorial/opencl_example_vector_soc/vector_add/bin/vector_add/top.map.smsg error: quartus prime analysis & synthesis was unsuccessful. 2 errors, 581 warnings  error: peak virtual memory: 1575 megabytes  error: processing ended: mon may 15 07:26:48 2017  error: elapsed time: 00:04:42  error: total cpu time (on all processors): 00:04:56 error (293001): quartus prime full compilation was unsuccessful. 4 errors, 581 warnings error: flow compile (for project /home/developer/workspace/opencl_intel_tutorial/opencl_example_vector_soc/vector_add/bin/vector_add/top) was not successful error: error: error(s) found while running an executable. see report file(s) for error message(s). message log indicates which executable was run last.   error (23031): evaluation of tcl script /home/developer/intelfpga_lite/16.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful error: quartus prime shell was unsuccessful. 11 errors, 581 warnings  error: peak virtual memory: 806 megabytes  error: processing ended: mon may 15 07:26:49 2017  error: elapsed time: 00:04:50  error: total cpu time (on all processors): 00:05:04  Google said that that "Error: Peak virtual memory: 806 megabytes" means that i´m using to much logic elements, but its just the vector-add example so I´m quite confused.  I hope someone can point out whats the problem.  Thanks :)

[Altera_Forum]

Your compilation is failing during synthesis which is very strange. Please post the output of the following commands: 

 aoc --version quartus_map --version  Also Terasic has two BSPs for this board. One is for Quartus v14.0, one is for v16.0. Which one are you using?  P.S. OpenCL in Quartus v16.1.0 is broken. Make sure you are using v16.1.1 or v16.1.2.

[Altera_Forum]

Tanks for repliying 

 aoc --version: Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler Version 16.1.2 Build 203 Copyright (C) 2017 Intel Corporation quartus_map --version: Quartus Prime Analysis & Synthesis Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition Copyright (C) 2017 Intel Corporation. All rights reserved.  I have installed the V16 BSP.  I had Quartus v16.1.0 installed and updated it to Version 16.1.2.203 today. But i got "compiler error, not able to generate hardware" again. I have the Quartus Prime Lite edition. Could this be a problem?   Since updating Quartus i´m not able to find the "quartus_sh_compile.log" do you know why this is the case?  Thanks for your help :)

[Altera_Forum]

That is strange. Have you tried removing the folder that is created by the OpenCL compiler? Do you get the "vector_add.log" file? 

I have not used the Quartus Prime Lite edition myself, but if you have a valid Quartus license, it is probably best to use the Standard version.

[Altera_Forum]

Yes, I have removed the folder before compilation. I have added the complete log-file because i couldn´t figure out where the error message is. 

Thanks for your help

[Altera_Forum]

I do not see any error messages in the log. Can you compress and post all of the OpenCL folder? You can remove non-log files if they are too big.

[Altera_Forum]

I couldnt upload the OpenCL folder because it was to large so I put it on dropbox, i hope you are able to open the folder. 

 https://www.dropbox.com/s/qaumfdyuqopop91/opencl_example_vector_soc.zip?dl=0

[Altera_Forum]

The "quartus_sh_compile.log" is actually inside the folder you uploaded. The final error message is the same as the one you posted earlier, but I found this in the log: 

 Critical Warning (138067): Current license file does not support incremental compilation. The Quartus Prime software removes all the user-specified design partitions in the design automatically.  I am not sure if this problem is actually from your license or Quartus Prime Lite. the feature comparison table on altera's website (https://www.altera.com/products/design-software/fpga-design/quartus-prime/download.html) claims that only Quartus Prime Pro supports "Incremental Optimization", but you certainly shouldn't need the pro version for your board. My recommendation is installing Quartus Prime Standard v16.0.2 (not v16.1.2) for maximum compatibility with your BSP and trying again. If you still faced the same error, contact Altera or Terasic directly.

[Altera_Forum]

Installing Quartus Prime Standard edition (Version 16.1.2) and using OpenCL SDK Version 16.1.0 solved the problem. 

Thanks for your help HRZ :)

[Altera_Forum]

That is good to hear, though I would strongly advise against using different versions of Quartus and AOC. For best experience, you should also install the 16.1.2 update for AOC.

[Altera_Forum]

--- Quote Start ---  Installing Quartus Prime Standard edition (Version 16.1.2) and using OpenCL SDK Version 16.1.0 solved the problem. Thanks for your help HRZ :)  --- Quote End ---    I have the same problem. I have following versions of openCL and Quartus. Should I update the version of OpenCL? Is there any command to update the OpenCL version?  Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler Version 16.1.0 Build 196 Copyright (C) 2016 Intel Corporation [krunal.patel@AOCLDev hello_world]$ quartus_map --version Quartus Prime Analysis & Synthesis Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition Copyright (C) 2017 Intel Corporation. All rights reserved.

[Altera_Forum]

--- Quote Start ---  I have the same problem. I have following versions of openCL and Quartus. Should I update the version of OpenCL? Is there any command to update the OpenCL version? (...)   --- Quote End ---   From the download center > intel fpga sdk for opencl (http://dl.altera.com/opencl/16.1/?edition=standard&download_manager=direct) open the Updates tab, download intel fpga sdk for opencl v16.1 update 2, change the file permission for the setup (.run) file by running the command: chmod +x *.run, and run the file.

[Altera_Forum]

I met the same issue. 

 I tried the combination of version with upgrade but still didn't work: 1. Quartus Prime Pro 16.1.0 and OpenCL SDK 16.1.0 2. Quartus Prime Pro 16.1.2 and OpenCL SDK 16.1.0 3. Quartus Prime Pro 16.1.2 and OpenCL SDK 16.1.2  The error in the log file "quartus_sh_compile.log" is as below:  Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design. Error (15744): In atom 'board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xc vr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g 3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_in st|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.i nst_twentynm_hssi_pma_rx_sd' Error (15744): The settings must match one or more of these conditions: Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != PCIE_GEN3_RX ) OR ( sd_output_off == CLK_DIVRX_14 ) Error (15744): But the following assignments violate the above conditions: Error (15744): sup_mode = USER_MODE Error (15744): prot_mode = PCIE_GEN3_RX Error (15744): sd_output_off = CLK_DIVRX_6 Error (18590): The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run. Error: design::import_design -file base.qdb -overwrite failed! Error (23031): Evaluation of Tcl script /root/intelFPGA_pro/16.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 11 errors, 0 warnings Error: Peak virtual memory: 4554 megabytes Error: Processing ended: Mon Sep 18 02:40:32 2017 Error: Elapsed time: 00:16:10 Error: Total CPU time (on all processors): 00:16:09   Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 1179 megabytes Error: Processing ended: Mon Sep 18 02:40:34 2017 Error: Elapsed time: 00:16:13 Error: Total CPU time (on all processors): 00:16:11  Did you solve the problem? Could you let me know how do you solve it?  Thank you!    --- Quote Start ---  From the download center > intel fpga sdk for opencl (http://dl.altera.com/opencl/16.1/?edition=standard&download_manager=direct) open the Updates tab, download intel fpga sdk for opencl v16.1 update 2, change the file permission for the setup (.run) file by running the command: chmod +x *.run, and run the file.  --- Quote End ---  

[SBoda]

And here is quartus_sh_compile.log

ERROR: packager tool failed to run. Check installation. Aborting compilation!