Help generating 65Mhz on DE2-115 Cyclone IV E in verilog

[Altera_Forum]

Hi, currently we have a FPGA project that will use VGA port and monitor. We are using altera DE2-115 Cyclone IV E board but the clock output is only 50Mhz..  

Because we dont have a monitor to support lower resolution our best choice is to use 1024x768 resolution with 65Mhz pixel clock the problem is the board clock only generates 50Mhz signal. So how can we generate 65Mhz clock signal? Thanks in advance.

[Altera_Forum]

Use a PLL, as available on the chip.