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Help needed in VHDl code for calculating the I and Q phase component for a ADC signal

Altera_Forum
Honored Contributor II
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Hello all, 

I am designing a DDC in which I need to calculate the In phase(I) and the Quadrature phase(Q) components of my ADC signal. I know how these components are manually calculated from some DSP tutuorials. But what I need to know is how can I represent the same through VHDL code, since I need to synthesise the code on a hardware basis. Just a small introduction on how to preoceed with this is appreciated. Right now, what I have done is I have synthesized the signals from NCO and I have performed the mixer operation (which is basically the multiplication operation of the ADC signal and the synthesizer output) and has completed the decimation by 8 process too. (I read from some tutorials that Decimation is a combo of Fir output + downsampling, and so I have performed it. Also divided the decimation output by 8 since its the decimation factor in my case). I have completed till this, and after this continues the calculation of I and Q phase components. Thanks in advance.
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Altera_Forum
Honored Contributor II
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You'd better to post your DSP block diagram. Most of DSP applications can be partitioned to separate blocks. Each of them can be coded manually or instantiated as a ready IP Core from Megawizard for example. 

Controller of DSP applications is rather simple, at least to control-dominated applications like a CPU.
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Altera_Forum
Honored Contributor II
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Hello,  

Thank for your reply. This is the DSP block diagram of my DDC. Help is appreciated. Thanks 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=12873
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Altera_Forum
Honored Contributor II
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Hi, 

What I actually require is to calculate the I and Q phase components from the digital output(bits) that I obtain after performing the decimation by 8 process(according to DDC.jpg). The output of my VHDL code after the decimation by 8 process is digital. So, a method for decomposing the digital output to I and Q phase components (also in digital) would be a lot more helpful. Please help me out to solve my issue. Thanks in advance.
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Altera_Forum
Honored Contributor II
1,078 Views

 

--- Quote Start ---  

Hi, 

What I actually require is to calculate the I and Q phase components from the digital output(bits) that I obtain after performing the decimation by 8 process(according to DDC.jpg). The output of my VHDL code after the decimation by 8 process is digital. So, a method for decomposing the digital output to I and Q phase components (also in digital) would be a lot more helpful. Please help me out to solve my issue. Thanks in advance. 

--- Quote End ---  

 

 

The I/Q you got is I/Q phase components. I am not clear what you are after.
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Altera_Forum
Honored Contributor II
1,078 Views

 

--- Quote Start ---  

The I/Q you got is I/Q phase components. I am not clear what you are after. 

--- Quote End ---  

 

Sorry its my fault. What I meant is that I have a digital output of a Decimated ADC signal from which I need to calculate the I phase and Q phase components for this signal.
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Altera_Forum
Honored Contributor II
1,078 Views

 

--- Quote Start ---  

Sorry its my fault. What I meant is that I have a digital output of a Decimated ADC signal from which I need to calculate the I phase and Q phase components for this signal. 

--- Quote End ---  

 

 

you have already done that at mixer output. 

 

However I am not clear about other things. how you process at such high sample rate after ADC
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Altera_Forum
Honored Contributor II
1,078 Views

 

--- Quote Start ---  

you have already done that at mixer output. 

 

However I am not clear about other things. how you process at such high sample rate after ADC 

--- Quote End ---  

 

 

Actually, in the decimation process, I reduce the sampling rate of the ADC signal by performing the decimation by 8, where the mixer output undergoes FIR filtering followed by down sampling by 8. Isn't this enough?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Actually, in the decimation process, I reduce the sampling rate of the ADC signal by performing the decimation by 8, where the mixer output undergoes FIR filtering followed by down sampling by 8. Isn't this enough? 

--- Quote End ---  

 

 

before decimation(after adc, at mixer) what is your clock speed and what is sampling rate
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

before decimation(after adc, at mixer) what is your clock speed and what is sampling rate 

--- Quote End ---  

 

 

sampling rate= 2.5 GHz and Clock speed= 1024 clock cycles/sec
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Altera_Forum
Honored Contributor II
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I assume you have typing mistakes in your last post as well as in your previous diagram.  

I don't want to move away from your original post but I asked about sampling rate after ADC i.e. input to mixer and clock speed there. 

By sampling rate I mean data sample rate at its given width (not bit rate).  

you also have 8 x something. is your data split up into 8 parallel streams or is that 8 independent channels of data. 

 

Without clear answers I really can't help
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Altera_Forum
Honored Contributor II
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I'm not clear about your problem. 

If you have the decimated output, you have the I/Q components, provided you have already multiplied your ADC signal in the mixer. 

Your ADC should go through Mixer, then through decimation process. IS it the correct order in your implementation? 

I guess that you mean you have no Mixer before decimation.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I'm not clear about your problem. 

If you have the decimated output, you have the I/Q components, provided you have already multiplied your ADC signal in the mixer. 

Your ADC should go through Mixer, then through decimation process. IS it the correct order in your implementation? 

I guess that you mean you have no Mixer before decimation. 

--- Quote End ---  

 

 

Hi, I have a mixer before decimation. But at the output, I have it as a single digital output from which I need to find the I and Q phase components separately. I mean like "111100011101010100..." something like this. I need to decompose this output into I and Q components separately. How to do this in VHDL. Can you suggest me any way of finding this out. Thanks in advance.
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