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Valued Contributor III
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Help with Verilog structure

Pardon the simple questions from a Verilog newcomer. 

 

I have three modules in a file. Compiles under Quartus OK. Load onto a Max V dev board and only the module designated as "Top" functions. Change "Top" to another module and it works however previous top does not. It seems only one "top" is allowed in Quartus. 

 

Verbiage on the web is muddy. Many online examples make no mention of a "top" module. I do not need multiple instantiates of any module.  

1. Should three modules compile and function without each having a declarative "top"module? 

2. If so how can each module be designated as a "top" in Quartus or at least be included in the output? 

 

 

Thanks in advance.
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Valued Contributor III
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1. The "top" module concept is something that quartus needs, and make sense if you think about it. Consider your design as a PCB. If you have 3 chips, and not "top" PCB to put them on, they are not going to work, as they wont be connected to one another. So Quartus needs this top to build the design. 

2. Write a new top level file that includes all 3.
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Valued Contributor III
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Unless you're building libraries or something it's always best practice to have one module per file and have the file name match the module name. Then, as Tricky said, create a new top-level file that instantiates and interconnects the three sub-modules and declare that as the top-level module in Quartus.

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