Hierarchical reference to custom type

Altera_Forum · ‎07-14-2016

I have a state machine defined with the following lines in one of my source files:

type SM_STATES is (idle, state1, state2, state3, state4);

signal current_state : SM_STATES;

In my testbench, I want to wait until this state machine has reached a certain state before allowing the test sequence to continue. I've tried various combinations of the following line of code, but can't get it to compile.

wait until <<signal .tb_top.u_top.u_state_machine.current_state : SM_STATES>> = state1;

I'm pretty sure I could move the type declaration to a package and then instantiate the package in my testbench, but that seems to be more of a workaround than true hierarchical reference. Does anyone know the correct syntax to check using hierarchical reference that the current state is state1?

Thanks - Much appreciated!

Altera_Forum · ‎07-14-2016

I normally do that by getting copy of state value as output from design

Altera_Forum · ‎07-14-2016

For hierarchical approach One can use signal spy. Here is an example I did years ago if it still applies! but I don't remember detailsed explanation


--Signal spy:
Library modelsim_lib;
Use modelsim_lib.util.all;
constant test_path   : string := "/my_tb/u1/adder1/"; -- path of modelsim units
signal spy_dout     : std_logic_vector (15 downto 0);         
signal spy_clk      : std_logic;
...
--spy port mapping
process
begin
   init_signal_spy(test_path & "result", "spy_dout",1);
   init_signal_spy(test_path & "clock", "spy_clk",1);
   wait;
end process;

Altera_Forum · ‎07-15-2016

What is the error? You will need to have SM_STATES type declared in a package so that you can see it in the testbench (Im not sure if you can use hierarchical references to fetch types outside of packages).

@Kaz - Signal spy is mentor's way of allowing hierarchical referencing in VHDL pre-2008. With VHDL 2008 you shouldnt need signal spy any more.

Altera_Forum · ‎07-15-2016

Ive just looked it up - external names can only fetch constants, shared variables and signals. So you need to make the type declaration visible by putting it in a package.

Altera_Forum · ‎07-15-2016

--- Quote Start ---

In my testbench, I want to wait until this state machine has reached a certain state before allowing the test sequence to continue.

--- Quote End ---

This is a red flag that you're not writing a proper testbench. In the real world, signals can only interact with other signals that are available on the interface. If you need to dive down into the design in order for the testbench to work, then you're not modelling how the system will actually work...which is kind of the whole point of a testbench.

Having said that, there are cases where it is handy to short circuit reality and make the internals visible to the testbench. A simple way is to define a package and put a copy of your signals in the package.

package magic_comms is
    signal copy_of_current_state : work.pkg_my_package.SM_STATES;
    ... other signals here if you want
end package magic_comms;
...
use work.magic_comms.all;
architecture rtl of my_design is
begin
    copy_of_current_state <= current_state;
    ... Other code, like the state machine that sets current_state
end rtl;
...
-- In the testbench
use work.magic_comms.all;
architecture rtl of my_testbench is
begin
    process(all)
    begin
        wait until copy_of_current_state=state4;
        ...
    end process;
end rtl;

Kevin Jennings

Altera_Forum · ‎07-18-2016

Thanks Tricky - I guess I'll go the package route.

In my model of "the real world", certain events take several seconds to complete. I'm shortening these events in the TB to get a reasonable simulation execution time, but want to have a gross check of the state machine in order to verify that the shortening of events was occurring correctly.