High-speed transmission interface at around 3 meters for FPGA to FPGA communication

[Scarlet]

Hi,

I’m looking for a high-speed transmission interface at around 3 meters for FPGA to FPGA communication.

My development environment:

• MAX10 10m08sae144c8g
• Quartus Prime Lite 23.1.1

Currently, I am considering options like LVDS and dividing the task into two parts:

1. Writing the transmission interface myself
2. Using the IP Catalog

Considering that I am new to the Intel FPGA development environment and not very familiar with Quartus Prime and the IP Catalog, I decided to first try writing the transmission interface myself. Here is my design:

LVDS Transmitter:

• Input: Enable
• Output: lvds_clk & lvds_data

LVDS Receiver:

• Input: lvds_clk & lvds_data
• Output: 12-pin IO

I have completed writing my transmission interface and confirmed the transmission signal using an oscilloscope and logic analyzer.

I am transmitting a fixed 12-bit data, but the receiving interface is still unable to correctly receive the data according to the transmitted signal.

(Using LVTTL to test the transmission and reception logic for now, not using the LVDS interface.)

This is my transmission signal:

My Verilog receiver module:

Receive data on the rising edge of lvds_clk.

(gpio_1、gpio_2 are just for my observation purposes)

module lvds_receiver (
	input wire clk,
	input wire reset,
	input wire lvds_clk,
	input wire lvds_data,
	output reg [11:0] data_out,
	output reg gpio_1,
	output reg gpio_2
);

	reg [3:0] loop = 0;
	reg [11:0] data_reg = 0;

	always @(posedge lvds_clk or negedge reset) begin
	
		if(!reset) begin
			data_reg <= 12'h0;
			loop <= 4'd0;
			gpio_1 <= 1'b0;
			gpio_2 <= 1'b0;
		end
		
		
		else begin
			
			if(loop == 4'd11) begin
				data_out <= {data_reg[10:0], lvds_data};
				loop <= 4'd0;
				gpio_1 <= ~gpio_1;
			end
			else begin
				data_reg <= {data_reg[10:0], lvds_data};
				loop <= loop + 1'b1;
				gpio_2 <= ~gpio_2;
			end
		end	
	end
	

endmodule

My ModelSIM simulations:

Transmit 0xABD (101010111101) and output to 12 pins in parallel after receiving.

FPGA self-transmission and self-reception simulations (FPGA to FPGA) of the transmission waveform :

But the actual results are different from the simulated ones.

My question:

1. I can’t figure out why the actual results and the simulation don’t match. I need help. Is there something I might have overlooked?

2. Regarding the use of the IP Catalog, I am still researching how to use the Soft LVDS IP. I haven’t found a detailed procedure for using this IP yet.

3. What interfaces can be considered for FPGA transmission over a distance of 3 meters?

[FvM]

Your receiver is missing a frame synchronization mechanism.

[Scarlet]

Indeed, I have found that there is no frame synchronization.

My initial judgment is that during FPGA power-up, it has led to a misjudgment of the rising edge of the LVDS clock.

I would like to ask if, generally, when using LVDS for transmission and reception, is it necessary to have a signal line to determine Enable?

[FvM]

LVDS is an IO standard, not a transmission protocol. If you use a SPI like protocol, you'll have clock, enable and data lines. You can also use UART style asynchronous protocol with start/stop bits. Or synchronous protocol with sync pattern. A popular method is 8b/10b encoding, receive clock derived from data stream by CDR circuit.

[Scarlet]

Yes, I understand that LVDS is only the Physical Layer in the OSI Model.

During the initial design, I found that there are synchronous methods involving a clock for transmission and asynchronous methods, like UART, that do not use a clock.

So, I designed a simple reception method. However, it seems to be encountering issues.

[Scarlet]

I can't believe it. Even though I added lvds_en for frame synchronization in the interface,

it still completes the reception on the rising edge of the 11th lvds_clk.

Below are my Verilog code and output results. What might I have overlooked?

module lvds_receiver (
	input wire clk,
	input wire reset,

	input wire lvds_en,
	input wire lvds_clk,
	input wire lvds_data,
	output reg [11:0] data_out,

	output reg gpio_1,
	output reg gpio_2
);
	reg [1:0] state;
	reg lvds_clk_prev;
	reg [3:0] loop = 4'h0;
	reg [11:0] data_reg = 0;

	
	parameter IDLE = 2'b00;
	parameter RX = 2'b01;
	parameter DONE = 2'b10;


	// lvds_clk_rising_edge
	wire lvds_clk_rising_edge = !lvds_clk_prev && lvds_clk;
	
	always @(posedge clk or negedge reset) begin
	
		if(!reset) begin
			state <= IDLE;
		end
	
		case(state)
			IDLE: begin
				if(!lvds_en) begin
					loop <= 4'd0;
					state <= RX;
				end
			end
			
			RX: begin
				lvds_clk_prev <= lvds_clk;

				// Check for rising edge of lvds_clk
				if (lvds_clk_rising_edge) begin
					data_reg <= {data_reg[10:0], lvds_data};
					loop <= loop + 4'd1;
					gpio_2 <= ~gpio_2;
				end
				// When 12 bits are received, update data_out and reset loop
				if (loop == 12) begin
					gpio_1 <= ~gpio_1;
					state <= DONE;
				end
			end
			
			DONE: begin
				data_out <= data_reg;
				if(lvds_en) begin
					state <= IDLE;
				end
			end
//			default: state <= IDLE;		
		endcase
	end

endmodule