I have worked mostly on Xilinix & In Xilinx Vivado latency information is available directly on the Synthesis report, But in Quartus i'm unable to find latency information anywhere. I'm new in FPGA field, so please if someone can guide me..
For Intel tools, timing related information, aka latency ,clocks, etc will get generated after the TIming Analyzer runs. This information will be present in the Timing Analyzer reports. The synthesis report will only provide information regarding the synthesis process and how the RTL is getting converted to logic gates, the mapping, etc.