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Altera_Forum
Honored Contributor I
1,001 Views

How OpenCL handles multiple accelerators on FPGA

Hi everyone, 

I would have two questions about how OpenCL manages multiple accelerators into FPGA:  

1) Can I access to two or more accelerators at the same time if I have only one PCIe bus? 

2) OpenCL is able to do partial reconfiguration into the FPGA when I have more than one accelerator?  

Thanks for your help 

 

Marco Montini
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8 Replies
Altera_Forum
Honored Contributor I
41 Views

1- What do you mean "one PCI-E bus"? For two (or more) accelerators, you need two (or more) PCI-E ports on your motherboard. As long as you have enough ports, you can use multiple accelerators. However, for all accelerators to run at full PCI-E speed, your processor/motherboard chipset must provide enough PCI-E lanes. 

 

2- The OpenCL runtime will see the two (or more) accelerators as separate devices. You will have to initialize the devices separately and create parallel queues for them. Then you can run the same or different kernels on the two board in parallel using one host code. Partial reconfiguration of the boards will likely be sequentialized automatically by Altera's OpenCL runtime.
Altera_Forum
Honored Contributor I
41 Views

Hi HRZ, 

maybe we didn't understand because for two accelerators I don't mean two different FPGA boards but two accelerator functions (kernels) inside the same FPGA. So for partial reconfiguration I mean that if launch a kernel into the FPGA and I want to execute another kernel, can I reconfigure the FPGA by replacing the first kernel with the second one or these kernels are static into the FPGA? I hope I am clear. Thanks for your help
Altera_Forum
Honored Contributor I
41 Views

Oh, I see. If you have multiple kernels inside the same ".cl" file, they will be synthesized as one FPGA bitstream and you can use them in parallel by creating multiple queues in the host and invoking each kernel from a different queue. But, if you have two different ".cl" files which are synthesized separately into different bitstreams, then you cannot use them in parallel since only one bitstream can be active on the FPGA at a time. You can, however, switch back and forth between multiple bitstreams in the same host code and the OpenCL runtime will automatically reconfigure the FPGA with the correct bitstream as long as the bitstream has been correctly loaded by the host code and each kernel is correctly associated with its respective bitstream.

Altera_Forum
Honored Contributor I
41 Views

Ok thanks. Therefore if I have one host code who executes two kernels (inside the same .cl file) with two command queues, first I execute one kernel and wait for reading the results and then the other kernel can be executed reconfiguring the FPGA dinamically. It may be correct? If yes, can the reconfiguration be set manually? Thanks for your helpful answers.

Altera_Forum
Honored Contributor I
41 Views

If they are in the same ".cl" file, then you will only have one bitstream which includes both kernels. In this context, you can use the kernels in parallel without needing to wait for one to finish to start the other one (unless there is a data dependency between them). In this case, there will be no need for dynamic reconfiguration either, since there is just one bitstream. 

 

Dynamic reconfiguration is only needed when you have more than one ".cl" file, which will give you more than one bitstream.
Altera_Forum
Honored Contributor I
41 Views

Ok perfect. Is there a particular sintax to do dynamic reconfiguration in case I have two .cl files?  

Thanks again for your help
Altera_Forum
Honored Contributor I
41 Views

I have never tried it myself, but it should work as long as you correctly load both bitstreams and create the kernel objects from the correct program object and the OpenCL runtime should automatically handle the dynamic reconfiguration whenever you enqueue a specific kernel.

Altera_Forum
Honored Contributor I
41 Views

Thanks for your answers because of are very useful.