How can I get FIR compiler II to generate verilog rather than VHDL files?

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How can I get FIR compiler II to generate verilog rather than VHDL files?

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I have used the FIR compiler II to generate a fir filter and I have specified the output to be Verilog. I have included its output .qip and .v files in a project that I am simulating using Aldec Active HDL. I am getting an Aldec license error because the top level filter file calls modules that only exist as VHDL modules, which my license doesn't support.

Is there any way to get equivalent verilog files from the FIR Compiler II?

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