Typically for RTL code, we can use chip planner in Quartus to see the resource place&route. My question is now I'm using commend aoc to generate the *.aocx file (aoc *.cl -o *.aocx). It will automatically go through compile, synthesis, place&route. Finally, when I open top.qpf, then click "chip planner", there is no place&route information but a blank FPGA chip. Is there any method to see the place&route on FPGA chip generated from OpenCL code? Many thanks.
OpenCL compilation does go through the similar stage for Place and route, but it is using the Partial Reconfiguration flow, so all the compilation steps are distributed in different revision. If you are really interested you may look through the compilation log file and open the specific revision to see the implementation details.
OpenCL development environment combines the HLD compiler and Quartus Prime abstracting the fpga details from the user.
I am wondering what you want to review the Chip Planner view ?
Unfortunately there is no way to "import" a placed-and-routed OpenCL design in Quartus while preserving the post-place-and-route information (or at least I couldn't find any). You will have to open the project generated by the OpenCL compiler (which can be used right after the first stage of OpenCL compilation, i.e. -c switch, is finished) and place and route it with Quartus manually to get such information. I tried it once with Stratix V and it worked. I am not sure about Arria 10, though, since, as MUsman said, that one uses Partial Reconfiguration.
Dear Arslan and HRZ,
Thank you so much for your help. Finally I got the place&route on Chip Planner. The reason I want to see chip planner is that I want to see each OpenCL kernel's corresponding physical position on the chip. Even though I got the overview of chip planner, I still can not tell which area belongs to which kernel. Is there any way to easily distinguish the area for different kernels? Maybe I should ask this question: Different kernels distributed in separate group of areas or tangled each other and cannot distinguished? Many thanks.
I don't think the OpenCL compiler puts any placement restrictions on the kernels; hence, the placer is allowed to put any part of any kernel on any section of the FPGA. In other words, a multi-kernel design will be placed and routed as a single design and I doubt it would be possible to tell the different kernels apart after placement and routing.