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Hi, all
I have build a NiosII processor with SOPC tool and find that the utilization of BRAM is not efficient. My target device is EC3C25 and its BRAM has 608256Bits, But I can use about 53%. If I want to increase the cache size of NiosII processor, QuartusII can not fit well and give error which show that project need more than 66 BRAM to fit. I think the root cause is the lack of interconnect resourse. Now the problem in front of me is that how can i optimize the interconnect and let me take good use of BRAM and result in good SOPC system performance. Good guide is appreciated! Thank you for you help!Link Copied
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to clarify, it sounds like you are trying to use a large portion of the block RAMs as an On Chip Memory for a Nios II processor. is that correct?
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Thanks thepancake for your reply, Just as your inferred, I really Build a on-chip memory by BRAM. For this case, Could you give me a good solution? Thanks again.
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the problem has to do with how Quartus fits block RAM for performance reasons, it doesn't seem to want to mux the output of the RAM blocks
my advice is to decrease the size of the on-chip RAM until it fits or else write your own optimized HDL RAM which will include output muxes and maybe pipelines. then import the HDL as a custom component- Mark as New
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note that ram %bit usage figure is very misleading. if the smallest block in your device is 9k bits then "use one single bit and the whole block is gone". ram blocks also have limitations on datawidth and if you wanted wider data then it connects several blocks together and may waste a large number of blocks. if you target optimum width you may save resource.
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that's true, but even if you count the number of RAM blocks in the device you'll run into no-fit based on the problem i described
for example the 3c25 has 66 M9K blocks. running each in 256x32 for a Nios system (so 16,896 words), you won't be able to use all 66 blocks unless you wrap your own RAM logic
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