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How can make DSPBuilder generate verilog?

Altera_Forum
Honored Contributor II
‎09-02-2009 02:00 AM
1,286 Views

Hello,  

 

When I use DSPBuilder to create a project and I want it to generate verilog, but it always generate VHDL. How can I set some parameter to get what I want.  

 

Thank you.
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Altera_Forum
Honored Contributor II
‎09-02-2009 04:00 PM
539 Views

DSP Builder can only generate VHDL.

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