How do I accomplish string manipulation during synthesis?

[Altera_Forum]

Hello everyone and thanks in advance for your replies. 

 Here's the situation. I coded up a fairly lengthy chuck of vhdl using std.textio.read and std.textio.write that parses up a couple of strings passed as generics into the entity. Now I know that textio is not synthesizable, but I used the statements in functions to interpret the strings and set constants in the entity. I just found out that the read / write functions are not executed at all. I could write my own version using 'new' and 'deallocate,' but those commands are not executed during synthesis either.   The one solution I have thought of is to use strings and integer index values as pointers and pass them back and forth. However, this is ugly to say the least.  Is there any other alternative that is VHDL only? Is there a pre-existing solution for this problem where read/write can be used in functions to set values for constants during synthesis?

[Altera_Forum]

The problem is that Quartus wont parse textio functions during synthesis (I dont think it will have anything to do with loading files in any way unless its a mif or hex file, and thats only inside the altsynram megafunction). I know brand X will. It also completly ignores access types. 

 I think the only way round this for you will be to write a TCL script that generates the constants for you.  Other than that - good luck!

[Altera_Forum]

Might be worth raising this via my support - if enough people ask for it maybe they'll start supporting it!

[Altera_Forum]

That's the response I thought I was going to get. I went ahead and converted everything to strings and integer indexing and lengths. It works fine but is not very elegant.

[Altera_Forum]

why not just wrap it up inside functions - hide away all the inelegent bits?