Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How do I cascade third PLL in my design?

FATTY_WANG
Beginner
616 Views

Hello,

 

I need to cascade the third iopll in my design.

Is it legal? I had ever seen the guidance that you could just cascade two pll.

 

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FvM
Valued Contributor III
600 Views

Hi,

the question title suggests that Quartus prevents double PLL cascading. Is it so?

Apart from this point, I didn't yet came across a situation where I had need to cascade three PLLs. What's the specific problem?

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AqidAyman_Intel
Employee
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From what I am aware of, there is mentioned in the user guide that the you can cascade a maximum of two PLLs. If I am not mistaken it is for Stratix 10 device.


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AqidAyman_Intel
Employee
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