How do I know the clock uncertainty and in/output delays?

[Altera_Forum]

Hi all, 

 To constrain my design, I suppose we need to constrain the clock uncertainty and input/output delays.  But how could I know what values should I put for set_clock_uncertainty(for example for a clock generated by pll) and input/output delays?  Thanks !

[Altera_Forum]

And there are three kinds of exceptions: false path, minimum/maximum delay, multicycle; 

 I know what're the first and last about. But when could the designer make a min/max delay exception? And what would be the delay values based on?

[Altera_Forum]

Just call derive_clock_incertainty. You shouldn't have to add uncertainty on top of that. 

Your I/O delays are based on what the I/O is hooked up to. If you drive an external device with a Tsu of 3ns, then you need a set_output_delay -max 3 applied to the port it drives. If the board delay to the device is 1ns and the board level clock is 0.5ns longer to the external device then the FPGA, then the value increases by 1ns but decreases by 0.5, for a new value of 3.5ns. Go to www.alterawiki.com and look at Popular Pages on the left. About the tenth one down is a TimeQuest User Guide that discusses a lot of this. Basically you set up clocks, which have a default setup and hold relationship. Multicycles are used to say the default relationship is not what you want, but something else based on the clock periods. set_min/max_delay constraints allow you to explicitly enter setup and hold relationships. They really shouldn't be used a lot. An example might be a resynchronization circuit of two registers synchronizing an asynchronous signal. They may run off a 4ns clock and hence have a 4ns setup relationship, but you might want to overconstrain this to 2ns since you know the first register is going metastable and you want to provide slack to let it settle.

[Altera_Forum]

OK! Thanks for your very helpful thread!