How do you launch "Memory Test" in Nios ii EDS command shell

[Altera_Forum]

Hello, 

 I'm trying to get the CFI interface to the Flash chip on the Altera cylone III development board working and I'm stuck because I'm unable to talk to the flash chip (or at least that is what I think) anyways, to keep this post simple I'll stick to just figuring out how to run this Memory Test tool. The Nios II Flash programmer users guide says around page 32 that you can run a "Test Flash" option in the Memory test software template. I have the "No CFI table found" error when I try to program my board and would like to try this flash tool out. How do you run this memory test application? I can't find it anywhere?

[Altera_Forum]

Hi, 

  --- Quote Start ---   I have the "No CFI table found" error when I try to program  --- Quote End ---   I guess you get problem with Flash.  To run without downloading to the flash : 1) To test memories with Altera programs,   you have to configure the FPGA with factory configuration (it is just a press button, or you can download via Quartus programmer) 2) You can run a software without downnloading programm to the flash :   In NIOS II IDE/SBT/EDS, you do "run as > ... hardware". By doing this, you download the programm to the RAM and run from here.  So, you can run the Altera memory test software  To create the diagnostic programm, in nios ii ide/sbt, create software from templates, you will find "hello world", "hello world small"....   To debug the Flash, you can laucnh a similar command in NIOS II Shell command :  nios2-flash-programmer --debug --base=0x0    --- Quote Start ---   Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Found CFI table in 16 bit mode Raw CFI query table read from device:  0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................  10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................  20: 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 00 Q.R.Y.....@.....  30: 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 00 ......'.6.......  40: 07 00 0A 00 00 00 03 00 05 00 04 00 00 00 17 00 ................ CFI query table read from device:  10: 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 07 QRY..@.....'6...  20: 07 0A 00 03 05 04 00 17 02 00 05 00 02 07 00 20 ...............  30: 00 7E 00 00 01 00 00 00 00 00 00 00 00 00 00 00 .~.............. CFI extended table read from device:  0: 50 52 49 31 33 08 02 01 01 04 00 00 01 B5 C5 02 PRI13...........  10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05 ................  20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................  30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ Read autoselect code 0001-227E (in 16 bit mode) No CFI override data for [FLASH-0001-227E] Device size is 8MByte Erase regions are:  offset 0: 8 x 8K  offset 10000: 127 x 64K Device supports AMD style programming algorithm Multi-byte programming with 32 byte buffer Sector erase timeout is 16s Word program timeout is 1ms Buffer program timeout is 4ms Leaving target processor paused   --- Quote End ---  

[Altera_Forum]

Hey Tsuchi, 

 Yea I've got the "No CFI table found at address 0x02000000" Here is a screen shot of what I'm seeing.  https://www.alteraforum.com/forum/attachment.php?attachmentid=8891     Im using Altera's Cyclone III development board. I'm only trying to talk to the flash part on there that is on the same bus as the SRAM. Here is a screen shot of my qsys. I'm connecting the CFI controller to the conduit bridge directly because I don't use the SRAM I don't think I need the pin sharer.   https://www.alteraforum.com/forum/attachment.php?attachmentid=8892   All I want to do is store my quartus Nios ii core AND my C code from the nios ii eds for that core so that when I power on the development board the FPGA runs BOTH my nios core WITH the C code I wrote for it. Basically I"m trying to get to the point where I turn on the board and it powers up running my c code for the nios ii processor without having to be programmed all the time. This board doesn't have the epcs device but rather a spansion flash part. I've read through most of the documentation and it sounds like you can do this with the nios ii flash programmer, but it seems I'm currently stuck on trying to communicate to this flash part.   My understanding was that I just build my quartus hardware project to include this CFI controller and the programmer should be able to talk to the cfi device. It looks like its almost working.  I've also attached the board reference manual for this development board. If you look at the flash section on the left under "onboard memory" it shows the memory map on page 2-60. In my qsys design my flash memory goes from 0x0200 0000 to 0x03ff ffff, but the memory map says the user space is only 32MB from 0x0200 0000 to 0x03F9 FFFF. I'm not sure what I should be doing here. Should I only be using the user space or should I be putting this design (the nios ii hardware design and software design) in one of the FPGA design spaces? Why does it show the address in qsys as using everything above 0x0200 0000?  Attached is the information regarding my flash part and it's control signals. I've verified all pin connections in pin planner are correct from fpga to flash via the signals generated with this qsys model so I am confident it isn't a pin to pin connection.  Control signals in qsys: https://www.alteraforum.com/forum/attachment.php?attachmentid=8896   Control signals in schematics: https://www.alteraforum.com/forum/attachment.php?attachmentid=8897

[Altera_Forum]

Update, Got flash working: 

 So I got flash working finally. I couldn't communicate to flash because of my memory address lines. It turns out that the nioss ii communicates to the memory in byte mode (at least this is my understanding) and since this flash part works with 16bit words I needed to leave off the least significant bit on the memory bus. Basically, I have a 25 pin address bus and so I needed 26 pins in for address in the Qsys flash controller. This allows me to leave FSA[0] disconnected and use FSA[1] -> FSA[25] basically matching up the word addressing of the flash part to "word" addressing of the nioss.  After doing this I now can see the CFI table and query information. Here is a screen shot of success:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8898     Now, I've programmed the nios ii .sof file and done the bsp to flash file conversion using the Nios II eclips eds and going to Nios II -> Flash programmer. This opens the flash programmer GUI. Here I go to new and select my BSP file and add it. After this I add the .sof file and the GUI generates the file generation command and the file programming command. I run this and it erases and programs successfully. The problem now is that when I reset the board it fails to program itself with the nios ii hardware (HDL) project. I can verify this because if I program the .sof with quartus the nios ii flash programmer can communicate with the flash part, but if I reset the board nothing can communicate with flash. I'm pretty confident this is because the nios ii processor is not getting loaded therefore there is no CFI controller to allow communication.

[Altera_Forum]

Please be concise. 

 How do you reset your board ? Off/ON or press button (or other input) ? You seem NOT to program FPGA with EPCS memory. You configure FPGA through JTAG : It looses its configuration at power off.  Have you set the reset vector at the Flash memory address in QSYS ?  Could you describe how do you manage your board configuration ? EPCS + FLASH or All (hardware + software) in FLASH or All in EPCS ? I hadly understand you

[Altera_Forum]

So I'm not sure exactly what was wrong, but I seem to have moved passed the memory overlap section. If anyone knows why that was happening don't hesitate to tell me, but I have figured out that when I use the nios flash programmer to convert my .sof file to flash and then program the flash file (hardware design) the dev board does not load it correctly. If I use quartus to convert my .sof file to a .pof file and program it that way it does load the hardware (nios) design correctly on power up. Basically programming the nios hardware design into flash with the nios flash programmer does NOT work and programming it with quartus as a .pof file DOES work. I don't understand why this is the case.

[Altera_Forum]

Hey guys.. I'm trying to execute a memory test template using nios 2. It is getting executed but I don't know what name i should give after selecting the CFI flash. I tries giving "/dev/cfi_flash_o" which is the flash that I have generated using sopc builder. 

I'm stuck here. please tell me what name i should give so that the cfi flash test runs successfully.  Thanks in advance!