How is accelerator frequency decided in OpenCL designs?

[mvemp]

If the opencl description contains multiple kernels connected with each other using channels, how is the frequency decided? Is it the kernel with least frequency? What about the frequency for isolated kernels (no communication to other kernels) in the same design? Does the frequncy depend upon the memory bandwidth of the FPGA board?

[Kenny_Tan]

It would be whole system. you can refer to

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_optimization_guide.pdf

1-21 to check on your performance bottleneck.

Thanks

[HRZ]

A quick summary:

• The same kernel clock is used for all kernels in the same CL file (which get placed and routed as one FPGA image). The operating frequency will be limited by the slowest kernel is the CL file. Whether the kernels are connected or not will not make a difference.
• Kernel operating frequency is not affected the external memory bandwidth of the FPGA, but the external memory bandwidth can be affected by the kernel operating frequency.