How often do you use Incremental Compilation?

[Altera_Forum]

Hello, I am thinking about using Incremental Compilation in my next design and wanted to see how many people are using IC in their Quartus designs. Those of you that have used it can you please share your comments - pros and cons? 

 Thank you, joe

[Altera_Forum]

I never use it. I have some bugs in several megafunctions when I use incremental compiling so now I always do a full compile.

[Altera_Forum]

Why are you using it? There are a lot of different things you can do with it, some of which I talk about here: 

http://www.alterawiki.com/wiki/tips_for_incremental_compilation_and_logiclock Those are all "non-standard" uses. The main thing it was supposed to help with was compile time, whereby you split your design into partitions(let's say 4 equal ones), set them all to post-fit, and when you make a change in only one of the partitions, that is the only one that needs to be synthesized and fit. The big problem is that for most designs, you need to floorplan(LogicLock) your partitions, to make sure they are on separate areas of the die and when only one is re-fit, it has a nice clean space to work in. (Some designs that aren't very full or easily meet timing can get away without those,). It's this floorplanning where things get difficult and the wheels often fall off. I've certainly seen users waste more time setting up a floorplan then they save in the end from Incremental Compilation. You can be successful with it, but it's not a guarantee. (Also note that having 3/4ths of the design locked down and only re-synthesizing, fitting 1/4th does not result in a compile time that is 1/4th of the original. You'd be lucky to have half. Sometimes there are other ways to reduce compile time, like turning down Physical Synthesis settings, for example) One last thing, and I mention this in the document, is incremental synthesis also saves compile time but is really easy. Just create some partitions and set them to post-synthesis. The synthesis time is reduced if you only change the logic in one partition, but the fitter re-fits everything from scratch. It's not nearly the compile time savings, but it's quick and easy and most likely to be successful. (You might get some compile time reduction just from the act of making partitions, as the partitions can be synthesized independently and are "shipped out" to different processors in a multi-processor system.)

[Altera_Forum]

I like Rysc's explanation. I tried a couple of times to venture down the path of IC. My intention was to lock down the large megafunctions such DDR controllers, xaui interfaces, qdr interfaces, etc. and then pass around the project to other team members. But that did not pan out very well. Generally, it was Altera's megafunction's that would have problems with this. E.g. the timing scripts would have problems, etc. 

 So now we just run a full compile. Using verilog macros we simply limit the functionality and therefore the module instances during development. Subsequently, we would run the full design. I used to think that we needed to develop better rules to write the logic but Rysc's post tells me that it not be all that beneficial.